臺灣博碩士論文加值系統

晶片封裝隨著晶片速度的提昇與系統晶片(System on a Chip: SoC)的發展趨勢，輸出輸入接腳之數目也相對增加，球格陣列(Ball Grid Array or Bump Grid Array：BGA)封裝於現今之趨勢要求體積輕薄短小、散熱快、電性佳之情況下，單位距離內必須容納更多的傳導線。然而高密度封裝，增加了傳導線間電性的問題，製程上的精密度及繁瑣，進而造成了封裝失敗(Failure)的機率亦不易找出失敗問題點發生之處。評估SoC構裝電性之問題，可由電壓源至接地間的SSN(Simultaneous Switching Noise,瞬間切換雜訊)、串音(Crosstalk)及阻抗匹配等來探討。而探討封裝失敗分析(FA：Failure Analysis)主要可分為破壞性分析及非破壞性分析兩類，然而破壞性分析以破壞封裝本體的方式來找出缺陷(Defects)落在之處，如去膠(De-capsulation)、研磨(Cross Section)等，因已破壞封裝本體，故其分析只有一次機會，必須花費較長時間來耐心完成。而非破壞性分析完全不會損害到封裝本體，如X-Ray、時域反射偵測儀(Time Domain Reflectometry：TDR)等，於分析後仍可保存樣本原始之狀況。
本研究探討高速封裝的電氣特性，應用時域反射偵測之步階反射訊
號來快速比較出不連續點或不均勻阻抗之處。使用IPA510擷取出等效模型，並與積體電路重點模擬程式(SPICE：Simulation Program with Integrated Circuit Emphasis: SPICE)所萃取的預測效能比對是否一致，來達到偵錯的參考依據。
由於缺陷的產生往往起因於不理想的製程參數，在此一併探討田口式實驗設計法(Experimental Design of Taguchi) ，以各參數關係的直交表配置，統計出一套最適當的製程參數。使本文針對SoC構裝故障模式提供更具體的解決方案。

Along with the rise time of signals becomes faster and a trend of SoC(System on a Chip). The input/output pin count is increasing in a package, and required high density of trace line or gold wire. But it is difficult to evaluate the best process parameter of assembly procedure, so that may cause some kinds of failure mode.
In this thesis, we will study how to detect fault location of electrical interconnection of BGA(Ball Grid Array) immediately, and evaluate optimum process parameter by Taguchi DOE(Design of experiment). Failure analysis(FA) including destructive and nondestructive method, we will compare the performance between common FA and TDR (Time Domain Reflectometry) approach. TDR is a FA tool because it can quickly perform nondestructive tests on packaged ICs.

誌謝....................................................……………………………………..I
中文摘要................................................………………………………….II
英文摘要................................................…………………………………IV
目錄....................................................…………………………………….V
圖目錄..................................................………………………………….VII
表目錄......................................................……………………………….XII
第一章 序言...............………………………………................................1
1-1 背景簡介......................................………………………………1
1-2 研究動機與目的................................…………………………..4
1-3 論文架構………………………………………………………..6
第二章 SoC構裝之傳輸線設計.................……………………………..7
2-1 SoC構裝傳輸線之基礎理論…………………………………8
2-1-1 特性阻抗及傳輸速度……………………………………8
2-1-2 集膚效應(Skin Effect)…………………………………..11
2-2 訊號傳送的問題.........................……………………...………12
2-2-1 串音..……………………………………………………12
2-2-1-1 互感與互容…………………………………………13
-V-
2-2-1-2 串音的雜訊分類……………………………………16
2-2-1-3 以等效電路模式模擬串音…………………………22
2-2-2 瞬間切換雜訊…………………………………………..28
2-3 以Polar軟體作SoC傳輸線模擬之探討……………………..30
第三章 故障模式分析...........................………………………………..33
3-1 一般故障模式的分析...............……………………………….33
3-1-1 非破壞性分析...............………………………………...34
3-1-2 破壞性分析...............…………………………………...39
3-2 以時域反射作故障模式分析.......................………………….41
3-2-1 時域反射分析分析儀.................……………………….42
3-2-2 等效電路之萃取…….................……………………….47
3-2-2-1 錫球區.................…………………………………..48
3-2-2-2 基板區.................…………………………………..49
3-2-2-3 銲線區.................…………………………………..51
3-2-3 以TDR實作故障分析...............……………………….52
第四章 製程參數設計....................…………………………………….61
4-1 參數設計的目的.............................…………………………...61
4-2 封膠製程參數設計.........................…………………………...61
-VI-
4-2-1注膠說明..........................……………………………….62
4-2-2模流分析............................……………………………...64
4-2-3 實驗計畫............................……………………………..66
4-2-3-1 田口式實驗計劃之基礎理論……………………..66
4-2-3-2 評估最佳化之作業參數…………………………..70
4-2-4 參數驗證與結論.................…………………………….78
第五章 結論..............................………………………………………...79
附錄.A BGA/FC封裝製程說明……….……………………………….81
參考文獻............................………………………………………………90
英文部份…………………………………………………………..90
中文部份…………………………………………………………..94

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中文部份
[C1] 謝金明，“高速數位電路設計暨雜訊防制技術”，全華科技圖書，初版三刷，民國92年7月。
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[C4] 鐘文耀，鄭美珠，“CMOS電路模擬與設計-使用HSPICE” ，全華科技圖書，初版一刷，民國92年9月。
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[C8] 袁帝文，王岳華，謝孟翰，王弘毅，“高頻通訊電路設計”，高
立圖書，初版三刷，民國91年9月。
[C9] 林定皓，“電路板機械加工技術”，台灣電路板協會，民國93年3月初版。
[10] 張耀文，”Physical Design for SoC”，國立台灣大學，民國91年4月。