本論文的目的，在於研製一個高品值因數(Q-Factor)且電感值可調的主動電感積體電路(Active Inductor Integrated Circuit)。此主動電感可被應用於無線通訊系統中、前端收發機(Front-end Transceiver)的模組裡面，這類模組如低雜訊放大器(Low Noise Amplifier)、壓控振盪器(Voltage Controlled Oscillator)…等。
主動電感之所以比螺旋式電感(Spiral Inductor)更加吸引人的地方在於所佔的晶片面積較小、有較高的Q值、以及可以調整的電感值。在本論文中，我們提出了一個使用ADS模擬出來的疊接組態主動電感，此電感之工作頻率為5.7 GHz，消耗功率為9.45 mW，最大的品質因數為40、而等效電感值最大可達24 nH，同時此主動電感也可以透過偏壓電流的調整，來達到不同的等效電感值。
為了證明上述主動電感確實可以應用在RFIC內，我們另外設計了一組使用主動電感的共源極疊接組態的低雜訊放大器。此放大器工作在5.7 GHz時，具有11.2 dB的增益、-15 dBm的 以及4.1 dB的雜訊指數。

The purpose of this thesis is to implement active inductor integrated circuits with a very high quality value and a tunable inductance. The active inductor can be extensively used in the application basic modules of front-end transceiver in wireless communication system, such as LNA (Low Noise Amplifier), VCO (Voltage Controlled Oscillator) … etc.
Because of the smaller area, the higher quality factor and the tunable inductance, active inductor exhibits charming characteristics that spiral inductor can’t exceed. The simulation results in the thesis show that a simple cascode active inductor can work at 5.7 GHz with 9.45 mW power consumption. It can deliver a maximum equivalent inductance of 24 nH with a maximum quality-factor of 40. Besides, the effective inductance and quality-factor can be tuned by controlling the bias current.
Using the above active inductor, a common-source low noise amplifier with an active inductor load is developed. The amplifier operates at 5.7 GHz with 11.1dB power gain, -15 dBm , and 4.1dB noise figure in simulation.

目 錄
第一章、緒論.........1
1.1簡介..............1
1.2論文架構簡介......2
第二章、電感 ...... 3
2.1被動電感..........3
2.2.1 螺旋電感(Spiral inductor)..... .........3
2.2.2 鎊線電感 (Bondwire inductor)...........5
2.2主動電感.................................. 6
2.2.1 主動電感簡介 ......................... .6
2.2.2 簡單疊接式(Simple cascode)主動電感..... 10
2.2.3具增益調節之疊接式主動電感.............. 11
2.2.4 主動電感RLC等效模型 ...................11
第三章、CMOS 5.7GHz 主動電感之設計 ..........14
3.1 TSMC 0.18um製程提供之螺旋電感模型量測.....14
3.2 簡單型5.7GHz疊接式主動電感之設計 ...........17
3.2.1 電路設計方法 .............................17
3.2.2 模擬結果.................................18
3.2.3 結果與討論 .............................20
第四章、低雜訊放大器(Low Noise Amplifier)......21
4.1 低雜訊放大器之效能參數 ....................21
4.1.1 MOS之雜訊模型推導 ....................22
4.1.1.1通道熱雜訊(channel thermal noise)........22
4.1.1.2分佈閘極電阻雜訊(distributed gate resistance noise)..22
4.1.1.3感應閘極電流雜訊(induced gate current noise)... 23
4.1.2雜訊指數.................................. 25
4.1.3諧波失真( Hormonic Distortion)...... .........29
4.1.4 1dB增益壓縮點( 1dB Compression Point) .........30
4.1.5三階截斷點 (third-order intercept point) .........31
4.2 LNA基本架構 ....................................33
4.2.1 電阻終端(resistive termination)組態 .........33
4.2.2共閘極(Common-gate)組態 ..................34
4.2.3 並串迴授(Shunt-series feedback)組態 .........35
4.2.4 源極電感退化(Source inductive degeneration)組態 35
4.2.5 疊接(Cascode)架構 ............................36
4.2.6 電流共用(current reuse)之低雜訊放大器 .........37
第五章、5.7GHz CMOS低雜訊放大器 ..................40
5.1 使用螺旋電感之5.7GHz CMOS LNA ..................40
5.1.1電路設計方法 ....................................40
5.2.2模擬結果 ....................................42
5.2使用主動電感之5.7GHz CMOS LNA ..................47
5.2.1電路設計方法 ....................................47
5.2.2 模擬結果 ....................................47
5.3結果與討論 ....................................52
第六章、結論 ....................................54
參考文獻 .............................................55

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