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研究生:鄭嘉文
研究生(外文):Chia-Wen Chen
論文名稱:降低功率及提高可測試度之高階合成方法
論文名稱(外文):High Level Synthesis for Low Power and Testability
指導教授:王行健
指導教授(外文):Sying-Jyan Wang
學位類別:碩士
校院名稱:國立中興大學
系所名稱:資訊科學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2004
畢業學年度:92
語文別:中文
論文頁數:45
中文關鍵詞:高階合成功率可測試度排程配置
外文關鍵詞:high level synthesislow powertestabilityscheduleallocation
相關次數:
  • 被引用被引用:1
  • 點閱點閱:168
  • 評分評分:
  • 下載下載:17
  • 收藏至我的研究室書目清單書目收藏:1
隨著科技的快速發展以及超大型積體電路製程的進步,人們將可以在相同的面積下,塞入更多的電晶體,也可以用更便宜的成本整合更多的功能於同一晶片中。但是由於封裝技術的限制以及接腳數的限制,電路的功能測試及驗證將日趨複雜,如此使得測試電路的成本卻相對的提高,所以如果能在設計電路的初期就提早考慮電路測試的問題,那麼將可以使得測試的成本大大降低,也可以提高電路的可測試率,同樣地,降低電路功率也是不可忽視的重要問題。
本篇論文主要著手於高階合成階段,提出一考慮電路可測試性與降低電路功率之排程與資源配置的方法,來減少電路中可能會發生較難測試的地方,並且在資源配置時盡量平均每個時間週期(time step)會發生切換活動的次數,以達成電路功率消耗降低的目標。於此方法中整體控制時序並不會增加,而且此方法並不需要額外增加掃描(scan)電路,所以可降低對電路面積的影響。
第一章 簡介 1
第一節 研究動機與目標 1
第二節 貢獻與成果簡述 2
第三節 內容大綱 2
第二章 背景知識與相關研究 4
第一節 行為模型 4
第二節 運算子之排程 5
第三節 變數的生命週期 7
第四節 資源配置 8
第五節 高階合成之流程 11
第六節 切換動作評估 12
第七節 相關研究 13
第三章 方法介紹與實作 15
第一節 演算法的概念 15
第二節 排程之演算法 15
第三節 配置之演算法 28
第四章 實驗結果 38
第五章 結論與未來工作 42
參考文獻 43
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