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研究生:李明源
研究生(外文):Lee Ming Yuan
論文名稱:低閘極電荷與高強健性金氧半場效電晶體之研究
論文名稱(外文):The Study of Low Gate Charge and High Ruggedness for New Power MOSFET Structure
指導教授:林泓均陳啟文陳啟文引用關係簡鳳佐簡鳳佐引用關係貢中元貢中元引用關係
學位類別:碩士
校院名稱:國立中興大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2004
畢業學年度:92
語文別:中文
中文關鍵詞:功率電晶體全面性離子植入NP井區自由感應切換
外文關鍵詞:POWER MOSFETBlanket ImplantNP- WELLUnclamped Inductive Switching
相關次數:
  • 被引用被引用:1
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本論文研究N-Type 60V DMOS (Double- diffusion process)功率電晶體的最佳化切換特性,以三種不同製程-傳統製程(Conventional Double-diffusion process),全面性離子植入(Blanket Implant)製程與NP井區(NP- WELL) 製程,所製作不同之元件結構進行最佳化的模擬,並且依模擬結果製作出上述三種元件,以驗證其切換特性及自由感應切換特性。模擬結果得到全面性離子植入結構與NP井區結構的閘極長度,比傳統結構較短33%,而同時可以維持在相同崩潰電壓(BVDSS)與相匹配的導通電阻值(Ron)。閘極長度縮短,可使閘極電荷(gate charge)降低 ,元件的切換速度加快,開關功率損失也較小。其中以NP井區結構的閘極電荷最低,元件的切換速度最快,切換特性也最好。
從元件模擬崩潰熱點(hot spot)位置之模擬可預先判斷三種不同製程功率半導體元件強健性之強弱,其中NP井區結構比其他兩種結構的強健性較好。
從自由感應切換測試電路進行模擬及實際量測,由模擬元件閘極耐衝脈時間(gate pulse time, tp)長短之比較,得到三種不同結構的雪崩崩潰能量之大小,其趨勢與實際量測數據結果一致。同樣的,NP井區結構可承受較大的崩潰能量,其強健性比傳統結構與全面性離子結構來的好。
Abstract
In this thesis, an N-type 60 VDMOS (double diffusion process) was studied to obtain an optimum switching and unclamped inductive switching characteristic. Three different DMOS devices structures with the optimum gate length fabricated by three different processes, conventional double diffusion process, blanket implantation (BI) process and NP- well process, were studied. It is observed that the gate length for blanket implant process and NP well process can be reduced by 33% while break down voltage and on resistant (Ron) still remain the same level. Among those devices, the NP well structure revealed the lowest gate charge and the best switching characteristic.
The hot spot simulation and unclamped inductive switching (test circuit) simulation on these three structures also indicate the NP well structure perform the best.
目 錄
誌 謝 Ⅰ
摘 要 Ⅱ
Abstract Ⅳ
目 錄 Ⅴ
圖 錄 Ⅶ
表 目 錄 Ⅸ
第一章 前言 1
第二章 元件的發展與原理 4
2.1 功率元件的應用與發展 4
2.2 功率金氧半場效電晶體的種類及演化 6
2.3 VDMOSFET結構與製程 7
2.4 元件崩潰原理 14
第三章 功率金氧半場效電晶體切換特性及最佳化模擬 31
3.1 功率金氧半場效電晶體的切換速度 31
3.2 模擬與實作 33
第四章 自由感應切換(unclamped inductive switching)特性 45
4.1 自由感應切換之定義與原理 45
4.2 自由感應切換(UIS)之失效機制 47
4.3 模擬與實作 49
第五章 結論與展望 64
參考文獻 66
圖 錄
圖2.1 功率元件之應用 17
圖2.2 功率元件之演化 18
圖2.3 (a)BJT(b)DMOS等效電路圖 18
圖2.4 水平式雙擴散金氧半場效電晶體截面圖 19
圖2.5 功率金氧半元件的種類圖 19
圖2.6 VDMOSFET截面圖 20
圖2.7 傳統 DMOS元件結構與導通電阻示意圖 21
圖2.8 功率電晶體在低壓與高壓之導通電阻比 22
圖2.9 VDMOS元件製程流程圖 26
圖2.10全面性離子植入結構剖面圖 27
圖2.11全面性離子植入結構雪崩電流路徑圖 28
圖2.12 NP井區結構剖面圖 29
圖2.13 NP井區結構雪崩電流路徑圖 30
圖3.1 (a)閘極電荷分佈圖與(b)MOS電容充放電效應圖 36
圖3.2 閘極電荷特性圖解(a)量測時間(b)外加電壓對閘極電荷
之影響(c)閘極電荷與電流關係(d)閘極電荷與電汲-源
極壓關係 37
圖3.3(a)閘極的上升時間(b)電容電路等效圖 38
圖3.4三種結構淨掺雜濃度之剖面圖 39
圖3.5 三種結構之閘級長度最佳化模擬結果 41
圖3.6三種結構之閘極電荷模擬曲線圖 42
圖3.7三種結構之實作電子顯微照片的側圖 44
圖4.1典型UIS測試線路圖 52
圖4.2 UIS測試之特性曲線圖 53
圖4.3功率電晶體等效線路與橫斷面 54
圖4.4主動型-雙載子激磁效應之模擬 55
圖4.5功率電晶體模擬晶片內部的晶格溫度變化等線圖 56
圖4.6 元件累增崩潰失效點之照片圖 57
圖4.7模擬三種元件結構熱崩潰點(hot spot)位置圖 58
圖4.8 UIS模擬之電性曲線圖 58
圖4.9 自由感應切換(unclamped inductive switching)測試電路之模擬
與實際量測波形 60
圖4.10元件所能承受之最大接面溫度之模擬圖 62
圖4.11自由感應切換測試電路雪崩崩潰之模擬特性曲線,崩潰
前後之特性曲線變化圖。 63
表 圖 錄
表一 製程參數與模擬數據 40
表二 三種結構的電性量測值 43
表三 UIS實驗量測值 59
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