近年來無線通訊產業發展快速，元件製造技術日趨成熟，使得整合數位、類比電路實現單晶片系統整合(SoC)的理想不再遙不可及，伴隨而來的新挑戰即為晶片內最難處理的時脈問題，其中包含了時脈同步和錯斜修正以及時脈調變等技術，都必更跟上晶片演進的步伐；有鑑於此，各架構之鎖相迴路應聲成為電路設計中主流焦點，且高精確度及多頻道切換功能之頻率合成技術亦廣泛被業界採用。本篇論文參考IEEE 802.11b/g標準規格，因應無線通訊系統要求的高線性度、高工作頻率去設計符合2.4GHz ISM頻帶之射頻前端電路中一關鍵組件∼頻率合成器；並於台積電(TSMC 0.35um CMOS 2P4M)所提供之製程技術完成晶片，再以NDL高頻量測實驗室提供的On-wafer量測完成實作之量測。論文中分別描述三個規格不同之高速前置除頻器，主體電路架構皆由CML Master-Slave DFF所組成，其中包括1.5GHz之除二電路、2.4GHz之除四除五電路以及2.4GHz之多模除頻電路(除數可從256到271，共15個通道)。論文最後再提出一個2.4GHz整數N多通道頻率合成器電路之設計模擬及下線實作。

For the wireless communication industry developing rapidly in recent years, the component manufacturing technology becomes ripe for integrating analog and digital circuits to realize system on a chip (SoC) no longer out of reach. The following new challenge is the clock problems inside the chip, including clock synchronization, deskew issue, and frequency modulation etc. In view of this, all kinds of phase-locked loops circuits become the major focus in the circuit design, and high accuracy and multi-channel synthesizer are adopted by the industry extensively. In this thesis, we discuss the circuit chips’ design of frequency synthesizer which meets the need of the IEEE 802.11b/g standard specification for the RF Front-end environment. All chips are implemented by the TSMC’s 2P4M, 0.35um CMOS technology, and measured by the On-wafer techniques which provided by the NDL’s RF group.
Moreover, we provide three different topologies of high speed Prescaler all constructed by Current Mode Logic Master-Slave DFF circuits , including 1.5 GHz Prescaler (divided-by-2), 2.4 GHz Prescaler (divided-by-4/5), and 2.4 GHz multi-modulus Prescaler ( divided-by-256~271). Finally, we propose a 2.4 GHz integer N multi-channel frequency synthesizer.

摘要 (中文) ………………………………………………………………i
摘要 (英文) …………………………………………………………… ii
誌謝 ………………………………………………………………………iii
目錄 ………………………………………………………………………iv
圖目錄 ……………………………………………………………………vii
表目錄 ……………………………………………………………………xii
第一章 緒論 ………………………………………………………………1
1-1 研究動機 ………………………………………………………1
1-2 論文組織 ………………………………………………………3
1-3 設計流程 ………………………………………………………4
第二章 無線通訊與鎖相迴路架構簡介 ………………………………… 5
2-1 無線通訊中鎖相迴路之應用 ……………………………… 6
2-1-1 無線通訊頻帶之應用 ………………………………………… 6
2-1-2 射頻收發機簡介 ……………………………………………… 8
2-2 “鎖相”之原理 …………………………………………… 11
2-3 電荷幫浦式鎖相迴路 ……………………………………… 12
2-4 數位比較迴路 ……………………………………………… 14
2-4-1 相位頻率偵測器 …………………………………………15
2-4-2 電流式充電幫浦 …………………………………………18
2-4-3 迴路濾波器 …………………………………………………… 20
2-5 壓控振盪器 ………………………………………………… 22
2-5-1 振盪器基本原理 ……………….……………………………… 22
2-5-2 振盪器特性 ………………………………………………… 26
2-6 鎖相迴路之應用電路 ………………………………………28
2-6-1 除整數與除小數之頻率合成器 ………………………………28
2-6-2 時脈與資料回復器 ……………………………………………32
第三章 前置除頻器電路設計 …………………………………………33
3-1 電路核心單元－電流模式D型正反器邏輯電路 ……………34
3-1-1 CML DFF操作方式………………………………………………35
3-2 電路輸出輸入緩衝級 ………………………………………36
3-3 前置除頻器電路實作 …………………………………………38
3-3-1 1.5G CMOS前置除頻器(除二) ………………………………38
3-3-2 2.4GHz CMOS 雙模前置除頻器(除四除五) ………………45
3-3-3 2.4GHz CMOS 多模前置除頻器(除256~271) ………………57
3-4 前置除頻器特性分析 ………………………………………65
3-4-1 靜態與動態架構分析 …………………………………………65 3-4-2 存鎖模式時間常數討論 ……………………………………...66
3-4-3 靈敏度圖形特性分析 ………………………………………..…70
第四章 頻率合成器電路設計 …………………………………………73
4-1 頻率合成器參數設定 ………………………………………74
4-1-1 鎖相迴路線性模型之數學分析 ……………………………….74
4-1-2 重要參數設定分析 ………………………………..…………81
4-1-3 相位雜訊來源分析 ……………………………………………85
4-2 頻率合成器設計與模擬 …………………………………..89
4-2-1 相位頻率偵測器 ………………………………………………..89
4-2-2 電荷幫浦 ………………………………………………………..90
4-2-3 迴路低通瀘波器 …………………………………..……………91
4-2-4 PFD/CP/LPF模擬結果 ..…………………………..……………92
4-2-5 LC壓控振盪器 ………………………………………………..95
4-2-6 電路佈局設計與預估規格 ……………………………………100
第五章 結論 ……………………………………………………………103

[1] Roland E. Best, “Phase-Locked Loops,” Design, Simulations, Fifth Edition, The
McGraw-Hall Companies, Inc, 2003.
[2] B. Razavi, “RF Microelectronics,” Upper Saddle River, NJ, Prentice Hall PTR,
1998.
[3] B. Razavi, “Design of Analog CMOS Integrated Circuit,” Mc Graw Hill,1996.
[4] B. Razavi, “Design of Integrated Circuits for Optical Communications”, Mc
Graw Hill,2003.
[5] David Johns, Ken Martin, “Analog Integrated Circuit Design”, John Wiley & Sons, inc, 1997
[6] T. H. Lee, “The Design of CMOS Radio-frequency Integrated Circuits”,
Cambridge University Press, 1998.
[7] IEEE Standard 802.11b: Higher-Speed Physical Layer Extension in the 2.4GHz
Band.
[8] Ching-Yuan Yang, Guang-Kaai Dehng and Shen-Iuan Liu, “High-Speed Divide -by-4/5 Counter for a Dual-Modulus Prescaler”, Electronics Letters, vol. 33, pp. 1691-1692, Sep. 1997.
[9] Ching-Yuan Yang, Guang-Kaai Dehng; June-Ming Hsu; Shen-Iuan Liu; “New
dynamic flip-flops for high-speed dual- modulus prescaler,” IEEE Journal of
Solid-State Circuits, vol. 33, no. 10 ,pp. 1568 —1571, Oct .1998.
[10] Hwan-Seok and Jinwook Burm Ohhata, “Comparative Study of Static and Dynamic D-type Flip-Flop Circuits using InP HBT’s,” IEEE Electron. Lett., vol. 28, pp. 2090-2091, 1992.
[11] Wohlmuth, H.-D.; Kehrer, D., “A 15 GHz 256/257 dual-modulus prescaler in 120 nm CMOS”, European Solid-State Circuits, ESSCIRC '03. Conference on , 16-18 Sept, pp. 77 — 80, 2003
[12] D. B. Leeson, “A Simplified Model of Feedback Oscillator Noise Spectrum,”
Proceedings of the IEEE, vol. 42, February 1965, pp. 329-330.
[13] Ching-Yuan Yang; Shen-Iuan Liu, “Fast-switching frequency synthesizer with a discriminator-aided phase detector,” Solid-State Circuits, IEEE Journal of , Volume: 35 , Issue: 10 , Oct. 2000, Pages:1445 — 1452
[14] Ram Singh Rana; Zhang Chen Jian, “A 2.4GHz Dual-Modulus Divide-by -127/128 Prescaler in 0.35um CMOS Technology,” Radio Frequency Integrated Circuits Symposium, IEEE, 2003
[15] Se-Yeob Kim, Soon-Seob Lee, Soo-Won Kim, and Tae-Geun Kim, “High Performance CMOS Dual-Modulus Prescaler Using Selective Latch Technique,” IEEE, 1999
[16] K.Mistry, W.Redman-White, J.Benson, and N.D’Halleweyn, “A high speed dual modulus divider in SOI CMOS with stacked current steering phase selection architecture,” Radio Frequency Integrated Circuits Symposium, IEEE, 2003
[17] George D. Vendelin, Anthong M. Pavio, Ulrich L. Rohde, “Microwave Circuit Design Using Linear and Nonlinear Techniques,” John Wiley & Sons, inc, 1990