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研究生:黃聖紘
研究生(外文):Sheng-Hong Huang
論文名稱:應用於主動式液晶顯示器之高效能緩衝放大器
論文名稱(外文):High Performance Buffer Amplifiers for AMLCD Applications
指導教授:張振豪
學位類別:碩士
校院名稱:國立中興大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2004
畢業學年度:92
語文別:英文
論文頁數:96
中文關鍵詞:液晶顯示器緩衝放大器迴轉率解析度
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本篇論文著重於可應用在大尺寸TFT-LCD源極驅動電路的輸出緩衝器之設計,並符合現今TFT-LCD高速,高驅動能力,高精確度與低功率消耗的需求。因此,我們設計了一個改良式的輸出緩衝放大器給UXGA使用。在此電路裡,我們在輸出端外掛一負載電容來模擬TFT- LCD源極映像點操作的狀態,且利用TSMC 0.35um 2P4M CMOS 製程的技術完成,並以SPICE 模擬其電器特性,工作頻率達100KHz,且輸出電壓可達全振幅的需求。
另外,本電路內將包含Nulling-input電路,來降低由於電路本身以及各個電路上元件不匹配的關係,所造成實際輸出值與理想值間之些微差距。因此,藉由此電路的使用,便可使輸出電壓與輸入端電壓的誤差值小於1mV。最後,因應LCD尺寸與解析度的提升,使傳輸資料線上的雜散電阻,電容值增加並使一列線所使用的時間縮短, 所以我們藉由新增一個預充電壓至影像信號電壓上,來補償其電阻電容延遲效應的問題,進而縮短其穩定時間。
This thesis focuses on the design of the output buffer for the TFT-LCD source driver circuit that is applied to the large-size panel. The design goals are high-speed, high driving capability, high precise and low-power consumption. Therefore, an improved output buffer used in the type of UXGA is designed. In the circuit, the operation of the pixel on TFT is simulated by using a loading capacitance at the output and the model of the TSMC 0.35um 2P4M CMOS technology. The driver circuit is simulated by the HSPICE program to get the electric characteristics. The operation frequency of the circuit is 100KHz and the full swing on the output voltage is achieved.
In addition, to reduce the difference between the practical and ideal values due to the mismatch effects of the circuit and devices, nulling-input part is included in this circuit. Thus, the error voltage is less than 1mV by using this circuit. Finally, owing to the increase of the size and the resolution of the TFT, it would increase the parasitic resistance and capacitance on the data line and shorten the one-row-line time. Therefore, we need to compensate the problem of the RC delay effect and shorten the settling time by adding a pre-emphasis voltage on the voltage of the video signal line.
TABLE OF CONTENTS
CHINESE ABSTRACT …………………………………………….. I
ENGLISH ABSTRACT …………………………………………….. II
ACKNOWLEDGEMENT ………………………………………….. III
TABLE OF CONTENTS ……………………………………………. IV
LIST OF FIGURES …………………………………………………. VII
LIST OF TABLES …………………………………………………... XIV
Chapter 1 Introduction …………………………………………….. 1
1.1 Background ………………………………………………………………... 1
1.2 Motivation …………………………………………………………….…… 1
1.3 Organization ……………………………………………………………….. 4
Chapter 2 Principles of LCD Driving ……………………………… 5
2.1 TFT-LCD Module Structure ……………………………………………….. 5
2.1.1 LCD Physics …………………………………………………………... 5
2.1.2 TFT Physics …………………………………………………………… 9
2.1.3 Pixel Design of TFT …………………………………………………... 14
2.2 Inversion Schemes …………………………………………………….…… 20
2.3 Crosstalk and Clock Feedback Effect ……………………………………… 23
2.4 Gamma Correction ………………………………………………………… 27
2.5 TFT-LCD Driver……………………………………………………….…… 28
2.5.1 Scan Driver…………………………………………………………….. 34
2.5.2 Data Driver ……………………………………………………….…… 34
Chapter 3 Design of Low Power and High Driving Output Buffer ……………………………………………………... 37
3.1 Introduction to The Output Buffer …………………………………….…… 37
3.2 Design Considerations of OP AMP ………………………………………... 40
3.3 Trends Toward of Output Buffer …………………………………………... 42
3.4 Operational Amplifier Structure …………………………………………… 49
3.4.1 Auto-Zeroing Compensation ………………………………………….. 50
3.4.2 Pre-Emphasis Driving Method ………………………………………... 56
3.4.3 OP with Auto-Zeroing and Pre-Emphasis Driving Method …………... 59
CHAPTER 4 The Implementation of The Output Buffer ……….. 61
4.1 Introduction ………………………………………………………………... 61
4.2 Proposed High Speed and High Driving Buffer Amplifier ………………... 61
4.2.1 Proposed I Buffer Amplifier …………………………………………... 61
4.2.2 Proposed II Buffer Amplifier …………………………………………. 65
4.3 Low Output Voltage Offset Buffer Amplifier ……………………………… 69
4.3.1 Operational Amplifier …………………………………………….…… 69
4.3.2 Bandgap Reference Circuit …………………………………………… 75
4.3.3 Auto-Zeroing Compensation Circuit ………………………………….. 80
4.3.4 Pre-emphasis Driving Circuit …………………………………….…… 81
4.3.5 OP with the Auto-Zeroing and the Pre-emphasis Driving Method …… 83
4.3.6 Summary ……………………………………………………………… 89
CHAPTER 5 Conclusion ……………………………………….…... 93
Bibliography …………………………………………………………... 95
List of Figures
Chapter1
Figure 1.1 TFT LCD Panel Structure ……………………………………………… 3
Figure 1.2 The resistance and capacitance diagram of the gate line …………….… 4
Chapter2
Figure 2.1 Illustration of the operation of by a 90° NW TN cell …………………. 6
Figure 2.2 T-V curve concerning TN and STN cells …………………………….… 7
Figure 2.3 Cross section view of TN or STN LCD ………………………………... 7
Figure 2.4 TFT-LCD panel structure …………………………………………….… 7
Figure 2.5 Three kinds of color filter ……………………………………………… 8
Figure 2.6 Passive matrix and active matrix LCD ………………………………… 8
Figure 2.7 The circuit of the integrated OLED TFT structure …………………….. 13
Figure 2.8 System on glass ………………………………………………………… 13
Figure 2.9 Clock feed-through effect ………………………………………………. 13
Figure 2.10 Threshold voltage and a life-span of the device for TFT …………….… 14
Figure 2.11 Parameters of Pixel Design …………………………………………….. 15
Figure 2.12 Signals applied to the bus-line at a given time ………………………… 16
Figure 2.13 TFT Operation as switch ……………………………………………….. 17
Figure 2.14 TFT I-V curve ………………………………………………………….. 18
Figure 2.15 Pixel Structure of TFT LCD ……………………………………………. 19
Figure 2.16 Pixel structure layout of TFT with Cs on common and Cs on gate ….… 19
Figure 2.17 Parasitic effect on signal bus-line design ……………………………… 20
Figure 2.18 Inversion schemes ……………………………………………………… 22
Figure 2.19 Crosstalk effect …………………………………………………………. 23
Figure 2.20 Diagram of pixel operation …………………………………………….. 26
Figure 2.21 Circuit diagram about Cs on common ……………………………….… 26
Figure 2.22 Diagram of pixel operation …………………………………………….. 26
Figure 2.23 Gamma correction ……………………………………………………… 27
Figure 2.24 The relationship between transparency and operation voltage of LC ….. 28
Figure 2.25 Block diagram of a LCD panel …………...…………………………….. 31
Figure 2.26 TFT-LCD driving system for XGA …………………………………….. 31
Figure 2.27 TFT LCD module …………………………………………………….… 33
Figure 2.28 Signals of TFT LCD ……………………………………………………. 33
Figure 2.29 Scan driver ……………………………………………………………... 34
Figure 2.30 Data driver ……………………………………………………………… 36
Figure 2.31 An example to the output voltage of DAC with gamma correction ……. 36
Chapter3
Figure 3.1 The structure of output buffer ………………………………………….. 39
Figure 3.2 Output buffer with dual input …………………………………………... 39
Figure 3.3 Architecture of output buffer …………………………………………… 44
Figure 3.4 A low-power, high-speed rail-to-rail output buffer …………………….. 45
Figure 3.5 Phase compensation using the capacitance load ……………………….. 46
Figure 3.6 Open-loop frequency characteristics …………………………………… 46
Figure 3.7 SR enhancement ………………………………………………………... 48
Figure 3.8 Implementation of slew rate enhancement ……………………………... 48
Figure 3.9 OP Amp ………………………………………………………………… 49
Figure 3.10 Architecture of operation amplifier ………………………………….…. 50
Figure 3.11 Timing Diagram of Source Driver IC ………………………………….. 51
Figure 3.12 OP Amp and its loading ………………………………………………… 51
Figure 3.13 Output error …………………………………………………………….. 54
Figure 3.14 Complete auto-zero scheme ………………………………………….… 55
Figure 3.15 Proposed auto-zero scheme …………………………………………….. 56
Figure 3.16 Illustration of RTC Mechanism ………………………………………… 57
Figure 3.17 The electrical model for the data line of TFT-LCD panel ……………… 58
Figure 3.18 The waveform of the pre-emphasis driving method …………………… 59
Figure 3.19 Timing diagram of the input and output data …………………………... 60
Chapter4
Figure 4.1 Schematic of the proposed I OP Amp ………………………………….. 62
Figure 4.2 AC simulation results of the proposed I OP Amp ……………………… 62
Figure 4.3 Op and its loading ……………………………………………………… 63
Figure 4.4 Simulate input and output of the proposed I OP Amp ……………….… 63
Figure 4.5 Simulate slew rate of the proposed I OP Amp ……………………….… 63
Figure 4.6 Layout of the proposed I OP …………………………………………… 64
Figure 4.7 Scheme of the proposed II OP Amp ………………………………….… 65
Figure 4.8 AC simulation results of the proposed II OP Amp ……………………... 66
Figure 4.9 Simulate input and output of the proposed II OP Amp ………………… 66
Figure 4.10 Simulate slew rate of the proposed II OP Amp ………………………… 66
Figure 4.11 Schematic of the CMOS current-mirror amplifier with SR enhance- ment……………………………………………………………………… 70
Figure 4.12 AC simulation results of the CMOS current-mirror amplifier …………. 70
Figure 4.13 Simulate the Buffer Amplifier with a 100KHz square input waveform (without slew rate enhancement part) …………………………………... 71
Figure 4.14 Zoom in the picture (Fig 4-9) at the rising edge (without slew rate en- hancement part)……………………………………………………….…. 71
Figure 4.15 Zoom in the picture (Fig 4-9) at the falling edge (without slew rate en- hancement part) …………………………………………………………. 72
Figure 4.16 The result of the output Buffer with a 100KHz square input waveform (with slew rate enhancement) …………………………………………... 72
Figure 4.17 The result of the output Buffer with a 100KHz variable input wave- form (with slew rate enhancement) ……………………………………... 72
Figure 4.18 Zoom in picture of the Fig 4-12 at the rising edge (with slew rate enh- ancement part)…………………………………………………………… 73
Figure 4.19 Zoom in picture of the Fig 4-12 at the falling edge (with slew rate en- hancement part)……………………………………………………….…. 73
Figure 4.20 Layout of the prototype chip ……………………………………………. 74
Figure 4.21 Structure of bandgap reference with curvature compensation ……….…. 77
Figure 4.22 Schematic of bandgap reference with curvature compensation ………… 78
Figure 4.23 AC simulation results of the Error Amplifier ………………………….. 79
Figure 4.24 Transient response ………………………………………………………. 79
Figure 4.25 Temperature dependence of the Bandgap Reference Circuit …………… 79
Figure 4.26 AC simulation results of the op by using the bandgap reference circuit.. 80
Figure 4.27 Proposed operational amplifier with the auto-zero port ………………... 81
Figure 4.28 OP by using the nulling-input circuit as Vin=4.5V ……………………... 81
Figure 4.29 Zoom in the picture Fig4-24 ……………………………………………. 81
Figure 4.30 OP Amp with pre-emphasis method and its loading ……………………. 82
Figure 4.31 Circuit configurations of driving circuit according to the sequences …... 83
Figure 4.32 The timing diagram of the clock signal ………………………………… 83
Figure 4.33 The transient response of output buffer and its loading ………………… 84
Figure 4.34 Simulate the OP on the rising edge (without pre-emphasis) ……………. 84
Figure 4.35 Simulate the OP on the falling edge (with pre-emphasis) ……………… 84
Figure 4.36 Simulate the OP on the rising edge (without pre-emphasis) ……………. 85
Figure 4.37 Simulate the OP on the falling edge (with pre-emphasis) ……………… 85
Figure 4.38 The rising edge input and output of the OP (without nulling-input) …… 86
Figure 4.39 The rising edge input and output of the OP (with nulling-input) …….…. 86
Figure 4.40 Layout of the OP with the pre-emphasis and the nulling-input part ……. 88
Figure 4.41 Timing diagram of the differential clocks ………………………………. 92
Figure 4.42 Timing diagram of the input and the output waveforms ………………... 92
Chapter5
List of Tables
Chapter1
Table 1.1 Comparison of different LCD types …………………………………….. 2
Chapter2
Table 2.1 Compare of color filter ………………………………………………….. 8
Table 2.2 Comparison between three types of TFT ………………………………... 12
Table 2.3 Comparison of the characteristic between LTPS and A-Si TFT LCD …... 14
Table 2.4 Specification of Panel …………………………………………………… 15
Table 2.5 Resolution of Display …………………………………………………… 15
Table 2.6 Comparison between four inversion for TFT …………………………… 22
Table 2.7 Comparison between three crosstalk for TFT …………………………… 24
Table 2.8 Comparison between the HSYN and VSYN ………………………….… 32
Chapter3
Table 3.1 Example of the output buffer with four inputs …………………………... 39
Chapter4
Table 4.1 Simulation Results for the proposed I OP Amp ……………………….… 64
Table 4.2 Simulation Results for the proposed II OP Amp ………………………... 67
Table 4.3 Comparison between the paper and the modified …………………….…. 68
Table 4.4 Comparison between the modified and the proposed I, II …………….… 68
Table 4.5 Comparison with the slew rate under the load is 470 pF and supply is 3.3V ……………………………………………………………………… 73
Table 4.6 Simulation Results for OP with slew rate enhancement part ………….… 74
Table 4.7 Comparison of the static current ………………………………………… 74
Table 4.8 Comparison of the power dissipation …………………………………… 80
Table 4.9 Compare the Slew-Rate with the differential condition ………………… 87
Table 4.10 Compare the Settling-Time with the condition of the Pre-emphasis ….… 87
Table 4.11 The relationship between the Vin and the Vref ………………………….. 88
Table 4.12 Corner case simulation results of the proposed I circuit ………………… 89
Table 4.13 Corner case simulation results of the proposed II circuit ……………….. 90
Table 4.14 Temperature dependency of the proposed I circuit ……………………… 90
Table 4.15 Temperature dependency of the proposed II circuit …………………….. 91
Table 4.16 Comparison the SR and one-row-line time between the different phases.. 92
Chapter5
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