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研究生:莊弘銘
研究生(外文):Hung-Ming Chuang
論文名稱:高性能多晶矽、擴散層電阻與異質結構場效電晶體之研究
論文名稱(外文):Investigation of High-Performance Polysilicon- and Diffused-Resistors and Heterostructure Field-Effect Transistors (HFETs)
指導教授:劉文超劉文超引用關係
指導教授(外文):Wen-Chau Liu
學位類別:博士
校院名稱:國立成功大學
系所名稱:微電子工程研究所碩博士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2004
畢業學年度:92
語文別:英文
論文頁數:188
中文關鍵詞:摻雜式通道場效電晶體雙通道多晶矽電阻擴散層電阻
外文關鍵詞:polysilicon resistordiffused resistordouble channelDCFET
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  在本論文的前半部份中,我們將討論自行對準矽化物的製程及非矽化金屬電阻在毫微米以下積體電路之應用。而在後半部份中,我們利用SILVACO Atlas模擬軟體以及低壓有機金屬化學氣相沉積法來研製新穎之砷化鎵異質結構場效電晶體。
  首先,我們探討雙重離子佈植法在鈦金屬矽化物之應用。所謂雙重離子佈植法是結合鍺(或砷)離子預先佈植法及矽離子混合法(Si ion-mixing)之技術,並不須增加額外的光罩;採用此雙重離子佈植法的技術,可以獲得比較低且穩定的n+型及p+型閘極及源/汲極鈦金屬矽化物電阻值;再者,對於使用雙重離子佈植法的樣本,其電阻值會比僅使用鍺(或砷)離子預先佈植法或矽離子混合法的樣本低5至10%;此外,雙重離子佈植法中的矽離子混合法可以降低因金屬矽化物製程所導致的PN接面反向漏電流增加的問題。另一方面,我們亦探討鍺(或砷)離子預先佈植法在鈷金屬矽化合物之應用。此外,我們亦將雙重離子佈植技術之鈦金屬矽化物及離子預先佈植之鈷金屬矽化物應用在0.2μm互補式金氧半導體(CMOS)元件中。
  接著,我們探討多晶矽層及擴散層電阻的電阻值特性。由於在次微米以下製程,為降低接點電阻,元件的各接點(Contact)均需採用矽化金屬製程,多晶矽層及擴散層電阻亦不例外;雖然多晶矽層及擴散層電阻之特性早已被廣泛討論,然而由於矽化金屬之存在及線寬之縮小,在回火時,多晶矽層及擴散層的摻雜物會因矽化金屬的影響而重新分布,使得電阻值特性隨之改變。我們以一簡單但實用的理論模型用於分析及計算非矽化金屬多晶矽層及擴散層的電阻參數,例如多晶矽電阻電性寬度(ΔW)、電性長度(ΔL)、介面電阻值(Rinterface)及本體電阻值(Rbulk)。此理論模式除了可以精確地計算非矽化金屬多晶矽層與擴散層的電阻值,亦可對多晶矽層及擴散層的電阻溫度係數(TCR)做一完整的探討。實驗結果顯示,此電阻模型與實驗數據相當吻合。
  接著,我們研究一種磷化銦鎵/砷化銦鎵/砷化鎵雙層通道結構之擬晶性通道摻雜式電晶體。使用雙層通道結構,可以分散因材料晶格不匹配所產生的應力,因此可以利用較厚且具有高銦含量的砷化銦鎵材料做為通道層,提昇閘極工作電壓擺幅及增加載子傳輸特性。我們利用二維的半導體模擬軟體Atlas模擬元件之各種特性,比較各種結構之元件特性差異。
  最後,我們以低壓有機金屬化學氣相沉積法研製此磷化銦鎵/砷化銦鎵/砷化鎵雙層通道結構之擬晶性通道摻雜式電晶體,我們利用平面摻雜層做為載子供應層,這可以使在雙層通道結構內的載子具有較佳的電子移動率,增加元件的直流及交流線性度。我們亦研究溫度效應對此元件之影響,並與模擬結果做一比較與討論。
  In this dissertation, the characteristics of self-aligned silicide (salicide) and non-silicide polysilicon- and diffused-resistors are demonstrated and studied. In addition, a new heterostructure field-effect transistor (HFET), grown by a low-pressure metal organic chemical vapor deposition (LP-MOCVD), is fabricated and investigated.
  First, the double ion-implant (DII) Ti-salicide process with the pre-amorphization implantation (PAI) and Si ion-mixing implant are developed and studied. The DII technique is combined by germanium (or arsenic) PAI and Si ion-mixing implant without additional lithography process. The sheet resistances of n+ and p+ polysilicon resistors with DII process are decreased especially in the narrow gate width regime. Based on this technique, the good performances of uniform Ti-silicide formation, low and narrow distribution of sheet resistances both on n+/p+ poly-gate and source/drain diffusion layers are obtained.   In addition, for DII process, the sheet resistances are lowered by 5 to 10% as compared to those of PAI or Si ion-mixing ones only. Furthermore, the junction leakage current is reduced when the Si ion-mixing process is employed. Experimentally, based on the studied PAI and Si ion-mixing techniques, high-performance 0.2μm CMOS devices are fabricated successfully.
  Second, the characteristics of non-silicide polysilicon- and diffused-resistors in sub-micron meter CMOS mixed-mode applications are studied. In order to reduce the contact resistance for sub-micron meter technology, the salicide process is required. Previously, some models related resistor characteristics have been reported. However, the presence of silicide and the decrease of line width cause the undesired phenomenon. A simple and useful model is proposed in this work to analyze and calculate some important parameters of polysilicon resistors including electrical delta W (ΔW), electrical delta L (ΔL), interface resistance Rinterface, and bulk sheet resistance Rbulk. In addition, the characteristics of temperature coefficient of resistance (TCR) are also studied. The theoretical analyses based on this model are in good agreement with experimental results.
  Third, an InGaP/InGaAs/GaAs double doped-channel heterostructure field-effect transistor (DDCHFET) is investigated. Based on the use of double channel structure, the stress force induced by the lattice mismatch can be reduced. Therefore, the thicker and higher In mole fraction of InGaAs layer can be used. Good carrier transport properties and wide voltage swing are obtained. A two-dimensional semiconductor simulation package Atlas is used to analyze DC and RF I-V characteristics of the studied device.
  Finally, a DDCHFET device, grown by a low-pressure metal organic chemical vapor deposition (LP-MOCVD), is fabricated and investigated. The employed double δ-doped sheets, as carrier supplier layers, are used to provide better carrier confinement in the InGaAs double channel layers and reduce the impurity scattering effect. Good DC and RF linearity are obtained. Also, the temperature-dependent characteristics are also studied. In addition, the DC and RF characteristics are in good agreement with theoretical simulations.
Abstract
Table Captions
Figure Captions
Chapter 1. Introduction …………………………………………………….. 1
Chapter 2. Characteristics of Silicide Resistors Prepared by
Double Ion-Implant (DII) and Pre-Amorphization
Implant (PAI) Techniques
2-1. Introduction ………………………….………….………………….. 6
2-2. Device Fabrication …………….…………….…….…….…………. 7
2-3. Experimental Results and Discussion …………….…..……….…… 8
2-3-1. The Sheet Resistance of TiSi2 and CoSi2 ….……..…….…………. 8
2-3-2. Reverse Junction Leakage Current ……………………………….. 12
2-3-3. Current-Voltage (I-V) Characteristics of MOSFETs …………........ 14
2-4. Summary …………………………………………………..……… 15
Chapter 3. Characteristics of Polysilicon- and Diffused-Resistors
3-1. Introduction ……………………………………………………….. 17
3-2. Device Fabrication ……………………….…….………….……… 18
3-3. Experimental Results and Discussion …………………………….. 19
3-3-1 DC Equivalent Circuit Model ……………………….……………. 19
3-3-2. Temperature Coefficient of Resistor (TCR) ……….……….……….. 23
3-4. Summary ………………………………………………………….. 26
Chapter 4. Theoretical Analysis of InGaP/InGaAs/GaAs Double
Doped Channel Heterostructure Field Effect
Transistors (DDCHFETs)
4-1. Introduction ……………………………………………………….. 28
4-2. Device Structure and Theoretical Considerations …….……….……. 30
4-3. Simulated Results and Discussion …………..….………….….….. 32
4-3-1. The Influence of δ-doped and Uniformly Doped Channels ………. 32
4-3-2. The Influence of δ-doped Sheet Density ………………………….. 36
4-3-3. The Influence of GaAs Spacer Thickness ……………….………... 40
4-4. Summary ………………………………………………………….. 41
Chapter 5. Characteristics of InGaP/InGaAs/GaAs Double Doped
Channel Heterostructure Field Effect Transistors
(DDCHFETs)
5-1. Introduction ……………………………………………………….. 43
5-2. Device Fabrication ………………….…….………..….….………. 44
5-3. Experimental Results and Discussion …………………………….. 45
5-3-1. DC Performances …………………………………………………. 46
5-3-2. Temperature-Dependent Characteristics ………………………….. 47
5-3-3. Microwave Characteristics ………………………………………... 51
5-3-4. The Comparison between Simulated Data and Experimental
Results …………………………………….………….…………… 52
5-4. Summary ………………………………………………………….. 53
Chapter 6. Conclusion and Prospect
6-1. Conclusion .………………….………………….………………… 55
6-2. Prospect .…………………………………………………………... 57
References ………………………………………………………………………… 59
Tables
Figures
Publication List
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