本論文主要研究應用於類神經網路圖形辨識、訊號準位排序、及模糊控制器的類比式階級處理電路。訊號階級處理電路包括最小值、最大值、中間值、贏者通吃、輸者通吃、多元贏者通吃、及任一階級之過濾辨識等。最小值或最大值的類比輸出可藉由一組類比開關從贏者通吃或輸者通吃的數位狀態輸出得到。
首先就現有傳統的贏者/輸者通吃電路架構作歸類與分析，探討其電路實現上之限制。我們利用自我回授機制加快電路的操作速度，設計出一個快速的輸者通吃電路。運作在8.3 MHz速度下，平均有15 mV 的辨識能力。並且突破製程偏移的限制，藉由單一比較器的概念，完成一個高穩定具可擴充能力的贏者/輸者通吃電路架構，並將其電路具體實現。此電路藉由單一的控制訊號，可規劃為贏者通吃功能或切換為輸者通吃功能，電路並具有加快速度之二層堆疊功能與寬廣的電壓供應範圍，能辨識10 mV 的輸入電壓差值。
但以上電路的功能只能處理訊號單一階級之辨識，為了在應用上更具彈性，此篇論文也設計出一個可規劃任意階級的過濾電路。並為了滿足次微米元件在低電壓運作的需求，提出電路工作電壓分別在1.2 V與 1 V的多功能階級過濾器，該過濾電路並同時具有多元贏者通吃功能。經量測實驗晶片在20 us 與4 us 反應時間下，分別具有40 mV 與100 mV 的辨識精確度。但此架構具有O(N2) 的複雜度，為了進一步降低架構的複雜度，我們提出一個隨著輸入變數個數增加，複雜度呈現線性成長的架構，此架構具有辨識 2 uA 電流差值的能力。且藉由基體驅動方式，亦成功的發展出一低電壓寬輸入範圍的多元贏者/輸者通吃電路。最後，藉由電容陣列、低壓開關、與互斥邏輯，實現了Hamming量測函數，並據以設計出一低壓相似性量測電路。搭配所設計出的贏者/輸者通吃電路，成功的模擬一個數位圖樣辨識系統，在輸入4x6圖素下，能辨識出每一個圖素差21 mV的電壓差值。本論文所提出電路的各項功能與文獻上重要電路相比較，顯示出本論文電路可允許在較低的電壓運作、較大的訊號輸入範圍、多元的階級處理功能、與對製程偏移有較高的穩定性。在應用與整合的考量下，具有較多優點與較佳彈性。

In this thesis, architecture designs and circuit realizations of CMOS analog signal rank-order processing are presented. Rank-order processing circuit is useful in pattern identification of artificial neural network, signals sorting, and fuzzy controller. Signal rank-order processing function includes minimum (MIN), maximum (MAX), median (MED), winner-take-all (WTA), loser-take-all (LTA), k-WTA, and arbitrary rank-order extraction. Analog output of MAX or MIN function can be obtained from the corresponding WTA or LTA digital output by using analog switches.
The operation and restriction of conventional WTA/LTA architectures are initially catalogued and analyzed. With regard to speed consideration, a new CMOS self-feedback LTA circuit operated 8.3 MHz with 15-mV identifiable capability on the average is arrived by measurement. With regard to reliability consideration, a scalable high reliable WTA/LTA circuit is achieved by utilization of a single-comparator architecture. WTA or LTA function is switchable by simple logic command. The circuit is expanded to two-layer architecture to further reduce response time, and it is also shown to have a wide supply voltage range. Measured result of an experimental chip has shown that 10 mV is distinguished.
Either WTA or LTA function, however, is only a single order operation. A new architecture for arbitrary rank-order extraction is designed. In CMOS sub-micro technologies, supply voltage of VLSI circuit is required to scale down in order to improve device reliability. A 1.2-V and a 1-V CMOS rank-order extractors with k-WTA capability are achieved in this thesis. Measurement results showed that the 1.2-V extractor with 40 mV resolution could operate successfully within 20 us. The 1-V extractor with 100-mV resolution is functional work within 4 us. One drawback of the extractors is that the number of the comparators required is proportional to the square of the number of inputs. The complexities of the architectures are O(N2) , where N is the number of input. In order to improve complexity, a rank-order extractor of O(N) complexity is analyzed and designed. The extractor is able to distinguish 2-uA difference among a set of input currents. Furthermore, based on bulk-driven technique, a 1-V wide-range k-WTA/k-LTA architecture is also developed, which is able to distinguish 5-mV input difference within 50 us.
Using these rank-order processing circuits and a low-voltage similar measurement (SM) circuit, one application for binary pattern identification is presented. Capacitor array, switches, and exclusive NOR gates realize Hamming function. Simulation results show the circuit responds a 21-mV difference for each one-pixel difference between two binary patterns of 4 x 6 dimension. Finally, these circuits compare with other designs in open literature. These circuits allow lower supply voltage, wider input range, multiple rank-order processing capability, and higher reliability. Depending upon application requirement and system integration, these proposed circuits have much specific advantages and a larger flexibility over conventional architectures.

CHAPTER 1 INTRODUCTION
1.1 Basic Concept ………………………………………………… 1
1.2 Organization of the Thesis ……………………………………… 6
CHAPTER 2 ANALOG WTA/LTA ARCHITECTURE
2.1 Architectures of Traditional WTA/LTA Circuits ………………… 7
2.2 Speed Improvement: A Self-Feedback LTA Circuit …………… 9
2.3 Reliability Improvement: A Highly Reliable WTA/LTA ………… 10
2.3.1 Operating Principle and Auto-Zero Comparator …………… 11
2.3.2 Architecture and Whole Operation ………………………… 15
2.3.3 Block Circuits ……………………………………………… 17
2.3.4 Design Consideration ……………………………………… 19
2.3.5 Expandability ……………………………………………… 20
2.4 Simulation and Measurement Results ………………………… 22
CHAPTER 3 LOW-VOLTAGE ARBITRARY RANK ORDER EXTRACTION
3.1 Principle of Rank-Order Extraction …………………………… 29
3.2 Architecture of Rank-Order Extraction ………………………… 31
3.3 1.2-V Rank Order Extractor ………………………………… 32
3.3.1 1.2-V Comparator ………………………………………… 32
3.3.2 Evaluation Cell ……………………………………………… 35
3.3.3 Design Consideration ……………………………………… 37
3.4 1-V Rank-Order Extractor …………………………………… 41
3.4.1 1-V Comparator …………………………………………… 42
3.4.2 Low-Voltage Analog Switch ………………………………… 49
3.4.3 Evaluation Cell Modification ………………………………… 51
3.5 Simulation and Measurement Results …………………………… 53
3.5.1 1.2-V Rank Order Extractor ……………………………… 53
3.5.2 1-V Rank Order Extractor ………………………………… 55
CAHPTER 4 ANALOG RANK-ORDER/k-WTA CIRCUITS OF O(N) COMPLEXITY
4.1 Algorithm of O(N) Complexity Rank-Order Extraction ……… 61
4.2 Architecture of Rank-Order Extraction ………………………… 62
4.2.1 Circuit Design and Analysis ………………………………… 63
4.2.2 Multi-Chip Expansibility for WTA/LTA …………………… 74
4.2.3 Accuracy Consideration …………………………………… 78
4.3 Architecture of k-WTA Function ……………………………… 80
4.3.1 Bulk-Driven Comparator …………………………………… 85
4.3.2 Block Circuit ………………………………………………… 87
4.4 Simulation and Measured Results ……………………………… 92
4.4.1 Rank-Order Extraction ……………………………………… 92
4.4.2 k-WTA Function …………………………………………… 97
CAHPTER 5 APPLICATION AND DISCUSSION
5.1 k-WTA for Length-L Rank-Order Identification ……………… 101
5.2 Identification of Binary Template Patterns ……………………… 102
5.2.1 Design of Low-Voltage Similarity Measurement Circuit ……… 103
5.2.2 Analysis of Non-Ideal Effects ………………………………… 106
5.2.3 Simulation and Measurement Results ………………………… 106
5.3 Discussion ……………………………………………………… 108
CHAPTER 6 CONCLUSIONS AND FUTURE WORKS
6.1 Conclusions …………………………………………………… 111
6.2 Future Works ………………………………………………… 113
REFERENCES …………………………………………………… 115

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