(3.237.20.246) 您好!臺灣時間:2021/04/16 08:43
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果

詳目顯示:::

我願授權國圖
: 
twitterline
研究生:吳燦輝
研究生(外文):Tsan-Huei Wu
論文名稱:應用於鎖相迴路之低成本的時脈抖動量測技術
論文名稱(外文):Low-Cost Jitter Measurement Technique for Phase-Locked Loops
指導教授:謝明得謝明得引用關係
指導教授(外文):Ming-Der Shieh
學位類別:碩士
校院名稱:國立成功大學
系所名稱:電機工程學系碩博士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2004
畢業學年度:92
語文別:英文
論文頁數:78
中文關鍵詞:鎖相迴路時脈抖動量測技術
外文關鍵詞:Phase-Locked LoopsJitter Measurement Technique
相關次數:
  • 被引用被引用:0
  • 點閱點閱:171
  • 評分評分:系統版面圖檔系統版面圖檔系統版面圖檔系統版面圖檔系統版面圖檔
  • 下載下載:26
  • 收藏至我的研究室書目清單書目收藏:0
  傳統量測時脈抖動的技術要量測到微秒(picosecond)的精確度需要非常昂貴的測試儀器。本篇論文提出了一種應用於鎖相迴路(Phase-Locked Loops)之低成本的時脈抖動量測技術。這提出的方法主要針對鎖相迴路對電源雜訊非常靈敏而且時脈抖動產生的主因來自於電源雜訊。在這提出的技術可以讓我們利用較低成本的測試儀器去量測時脈抖動。

  本篇論文研究的方向就是去發展一套有效分析時脈抖動的方法。我們直接在所定義的“時脈抖動時域”下去處理時脈抖動,進而取代傳統處理時脈抖動所用的“相位時域”。當在電路層次(Circuit-Level)模擬時運用這個方法可以讓我們非常容易的去觀察並且分析時脈抖動的行為。最後一個運用“時脈抖動時域”原理所發展而成的內建式之鎖相迴路的時脈抖動量測電路被提出來而且驗證。
  Accurate measurement of jitter to picosecond accuracy using conventional methods requires very high-cost test instrumentation. In this thesis, we present a low-cost technique for jitter measurement of phase-locked loops (PLLs). The proposed approach exploits the high sensitivity of PLL’s jitter to power supply variations, and is applicable to PLLs whose jitter is predominantly due to power supply noise. The technique enables the potential of using of a medium-accuracy tester for the production test of PLL’s jitter.

  The aim of this thesis is to develop an efficient methodology for analyzing jitter. Instead of describing the jitter in the traditional phase domain, we deal with the jitter directly in the defined “jitter domain”. In this manner, it becomes much more easier to observe and then analyze the behavior of jitter at the circuit-level simulation. After that a simple on-chip PLL’s jitter measurement circuit, which utilizes the jitter-domain principle, is proposed and demonstrated.
CHAPTER 1 Introduction.........................1

1.1 Motivation.................................1

1.2 Organization of Thesis.....................2

CHAPTER 2 Background and Previous Work.........4

2.1 Background.................................4

2.1.1 Basic PLL Architecture and Operational
   Principle................................4

2.1.2 Linear Phase-Domain Model................6

2.1.3 Noise Transfer Function.................12

2.1.4 Jitter..................................13

2.2 Previous Work on PLL Testing..............18

2.2.1 Structural Test.........................18

2.2.2 Functional Test.........................21

CHAPTER 3 Design of Phase-Locked Loops........24

3.1 Overview..................................24

3.2 Phase-Frequency Detector..................26

3.3 Charge-Pump Circuit.......................31

3.4 Loop Filter...............................33

3.5 Voltage-Controlled Oscillator.............36

3.6 Frequency Divider.........................41

3.7 Simulation Results........................42

CHAPTER 4 Proposed Technique for Jitter
      Measurement.......................44

4.1 Jitter-Domain Model of PLLs...............45

4.1.1 Jitter-Domain Model for VCO.............46

4.1.2 Jitter-Domain Model for FD..............57

4.1.3 Jitter-Domain Model for PFD.............64

4.2 Low-Cost Jitter Measurement Technique.....68

CHAPTER 5 Conclusions and Future Work.........75

5.1 Conclusions...............................75

5.2 Future Work...............................76

References....................................77
[1]W.H. Lee, J.D. Cho and S.D. Lee, “A High Speed and Low Power
Phase-frequency Detector and Charge-pump,” Asia and South Pacific Design
Automation Conference, pp. 269 - 272, vol. 11999, Jan. 1999.


[2]K.H. Cheng, T.H. Yao, S.Y. Jiang and W.B. Yang, “A Difference Detector
PFD for Low Jitter PLL,” IEEE International Conference on Electronics
Circuits and Systems, pp. 43 - 46, vol.1, Sep. 2001.


[3]Y. Furukawa, M. Kimura, M. Sugai, S. Kimura, and M. Purtell, “Jitter
Minimization Technique for Mixed Signal Testing,” International Test
Conference, pp. 613 - 619, Sep. 1990.


[4]M. Mansuri and C.K. Ken, “Jitter Optimization Based on Phase-locked Loop
Design Parameters,” IEEE Journal Solid-State Circuits, pp. 1375 - 1382,
vol. 37, Nov. 2002.


[5]J.A. McNeill, “Jitter in Ring Oscillators,” IEEE Journal Solid-State
Circuits, pp. 870 - 879, vol. 32, Jun. 1997.


[6]J.A. McNeill, “A Simple Method for Relating Time- and Frequency-domain
Measures of Oscillator Performance,” Southwest Symposium Mixed-Signal
Design, pp. 7 - 12, Feb. 2001.


[7]F. Azais, Y. Bertrand, M. Renovell, A. Ivanov and S. Tabatabaei, “An
All-digital DFT Scheme for Testing Catastrophic Faults in PLLs,” IEEE
Design & Test of Computers, pp. 60 - 67, vol. 20, Jan. 2003.



[8]K. Seongwon and M. Soma, “An All-digital Built-in Self-test for
High-speed Phase-locked Loops,” IEEE Transactions on Circuits and
Systems II: Analog and Digital Signal Processing, pp. 141 - 15, vol. 48 ,
Feb. 2001.


[9]S. Kim, M. Soma and D. Risbud, “An Effective Defect-oriented BIST
Architecture for High-speed Phase-locked Loops,” IEEE VLSI Test
Symposium, pp. 231 - 236, Apr. 2000.


[10]S. Sunter and A. Roy, “BIST For Phase-locked Loops in Digital
Applications,” International Test Conference, pp. 532 - 540, Sep. 1999.


[11]P. Goteti, G. Devarayanadurg and M. Soma, “DFT for Embedded Charge-pump
PLL Systems Incorporating IEEE 1149.1,” Proceedings of the IEEE Custom
Integrated Circuits Conference, pp. 210 - 213, May 1997.


[12]T. Xia and J.C. Lo, “On-chip Jitter Measurement for Phase Locked
Loops,” IEEE International Symposium on Defect and Fault Tolerance in
VLSI Systems, pp. 399 - 407, Nov. 2002.


[13]F. Herzel and B. Razavi, “A Study Of Oscillator Jitter Due to Supply
and Substrate Noise,” IEEE Transactions on Circuits and Systems II:
Analog and Digital Signal Processing, pp. 56 - 62, vol. 46, Jan. 1999.


[14]R. Voorakaranam and A. Chatterjee, “Low-cost Jitter Measurement
Technique for Phase-locked Loops,” IEEE Midwest Symposium on Circuits
and Systems, pp. 956 - 959, vol. 2, Aug. 2000.


[15]T.J. Yamaguchi, M. Soma, L. Malarsie, M. Ishida and H. Musha, “Timing
Jitter Measurement of 10 Gbps Bit Clock Signals using Frequency
Division,” IEEE VLSI Test Symposium, pp. 207 - 212, May 2002.


[16]C.C. Tsai and C.L. Lee, “An On-chip Jitter Measurement Circuit for the
PLL,” Asian Test Symposium, pp. 332 - 335, Nov. 2003.


[17]A.H. Chan and G.W. Roberts, “A Synthesizable, Fast and High-resolution
Timing Measurement Device using A Component-invariant Vernier Delay
Line,” International Test Conference, pp. 858 - 867, Nov. 2001.


[18]A.H. Chan and G.W. Roberts, “A Jitter Characterization System using A
Component-invariant Vernier Delay Line,” IEEE Transactions on Very Large
Scale Integration Systems, pp. 79 - 95, vol. 12, Jan. 2004.


[19]K.H. Cheng, S.Y. Jiang and Z.S. Chen, “BIST for Clock Jitter
Measurements,” International Symposium on Circuits and Systems, pp.
V-577 - V-580, vol.5, May 2003.
連結至畢業學校之論文網頁點我開啟連結
註: 此連結為研究生畢業學校所提供,不一定有電子全文可供下載,若連結有誤,請點選上方之〝勘誤回報〞功能,我們會盡快修正,謝謝!
QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top
無相關論文
 
1. [14] 杜玉振,「高失業率情勢的內涵與因應」,信用合作,第51期,民國86年,45-50頁。
2. [17] 林桂碧、狄明德,「從失業現象探討台灣地區發展第三部門就業方案之需要性(下)」,勞資關係月刊,第20卷第10期,民國91年,40-48頁。
3. [16] 林桂碧、狄明德,「從失業現象探討台灣地區發展第三部門就業方案之需要性(上)」,勞資關係月刊,第20卷第9期,民國91年,38-48頁。
4. [15] 林佩芬,「失業潮下的中年轉業危機」,就業與訓練,第19卷第3期,民國90年,68-72頁。
5. [19] 邱秋瑩,「當前台灣失業率攀升之分析與對策」,自由中國之工業,民國91年6月,1-44頁。
6. [13] 李漢雄、馬素慧,「探討當前中高齡者就業問題」,就業與訓練,第19卷第1期,民國90年,7-11頁。
7. [10] 李誠,「評述現階段臺灣的結構性失業問題」,經濟前瞻,第45期,民國85年, 126-130頁。
8. [6] 江豐富,「中高齡基層勞工之失業問題與因應對策」,自由中國之工業,第91卷第7期,民國90年,41-81頁。
9. [8] 邱志洲、李天行、林凡群,「台北市失業率之預測----模糊時間序列之應用」,輔仁管理評論,第5卷第2期,民國87年9月,177-196頁。
10. [40]趙文璋,「當前國內失業情況及勞動市場供需結構變化研析」,今日合庫,第23卷第2期,民國86年,88-95頁。
11. [39]張瀞云,「全球化與臺灣勞動受雇結構轉變」,經濟情勢暨評論,第6卷第4期,,民國90年,87-96頁。
12. [38]張聖英,「臺灣地區失業率與經濟變遷之研析」,主計月刊,第559期,民國91年,102-113頁。
13. [37]張敬學,「當前我國經濟景氣、失業與外勞」,今日經濟,第344期,民國85年,30-37頁。
14. [31]黃仁德,「臺灣地區人口結構變動對失業率的影響1978-1990年」,人口學刊,第15期,民國81年,61-76頁。
15. [25]孫志麟,「高等教育與就業:臺灣現象的分析」,教育研究資訊,第4卷第6期,民國85年,129-142頁。
 
系統版面圖檔 系統版面圖檔