語音翻譯是未來語音與語言技術一個重要的應用，本篇論文提出一個基於ARM微處理器的可程式化系統晶片設計應用於可攜性的語音翻譯，此可程式化系統晶片具有小面積、低成本、即時處理、高可靠度與具靈活性的特性，我們利用一個例句式模板檢索演算法來加快處理速度與節省記憶體需求量，在所提出的語音翻譯可程式化系統晶片設計中，包含了基於AMBA匯流排的可程式化系統晶片架構設計、數位/類比轉換電路設計(包含類比印刷電路板與數位控制電路矽智產)、模板檢索矽智產設計與系統中之軟體處理程序設計，並將整個設計實現於ALTERA公司的EPXA10F1020C2發展平台，在40 MHz的工作時脈下，ㄧ個100句模板的翻譯動作將會在0.5秒內完成，此系統的最大頻率可達46.22 MHz，使用的邏輯元件為19,318 (佔EPXA10全部邏輯元件的50%)。

　　Spoken language translation is a prospective application of speech and language technology. This thesis presents an ARM-based system on a programmable chip (SOPC) design for a portable spoken language translation application. This SOPC is characterized by small size, low cost, real-time operation, high reliability and flexibility. We adopt the example-based template retrieval algorithm to speed up process and to reduce memory requirement. For SOPC realization of the proposed SLT system, this work designs the AMBA-based SOPC architecture, the AD/DA conversion circuit (include analog PCB and logic controller IP), the template retrieval IP and the software procedures of the SOPC. We implement the entire design with ALTERA EPXA10F1020C2 device. The translation process can be completed within 0.5 second at a 40 MHz clock frequency while the number of templates is 100. The maximum frequency is 46.22 MHz, and the usage of logic elements is 19318 (50% of the total logic elements of EPXA10 device).

中文摘要...........................................................i
ABSTRACT..........................................................ii
ACKNOWLEDGMENTS..................................................iii
LIST OF FIGURES..................................................vii
LIST OF TABLES.....................................................x

CHAPTER 1 INTRODUCTION............................................1
1.1. Introduction to Spoken Language Translation................1
1.2. Motivation.................................................3
1.3. Framework of the Proposed System...........................3
1.4. Organization of Thesis.....................................7

CHAPTER 2 THE PROPOSED SOPC ARCHITECTURE..........................8
2.1. Overview of the SOPC Development Board.....................8
2.1.1. AlteraTM ExcaliburTM EPXA10 Development Board..............8
2.1.2. ARM-based ExcaliburTM Device..............................10
2.2. Hardware/Software Partitioning............................12
2.3. Hardware Architecture of the SOPC for Spoken Language
Translation system........................................14

CHAPTER 3 HARDWARE/SOFTWARE CO-DESIGN............................16
3.1. Analog-to-Digital / Digital-to-Analog Converter...........16
3.1.1. Description of the Converter Board and the Controller.....16
3.1.2. Analog Circuit of ADC/DAC.................................19
3.1.3. Digital Circuit of the Controller.........................20
3.1.4. Timing Diagrams between Advanced High-performance Bus
and Advanced Peripheral Bus...............................22
3.2. Template Retrieval IP Design..............................23
3.2.1. Description of Template Retrieval IP......................23
3.2.2. Data Flow Projection......................................26
3.2.3. Hardware Design of the Template Retrieval IP..............29
3.2.4. The Controller Design.....................................35
3.3. Memory Allocation.........................................38
3.4. Software Procedure........................................40
3.4.1. Speech Signal Preprocessing...............................40
3.4.2. Pattern Extraction Procedure..............................42

CHAPTER 4 IMPLEMENTATION AND VERIFICATION........................48
4.1. Implementation of AD/DA Conversion Circuit................49
4.1.1. Implementation of the ADC/DAC Circuit Board...............49
4.1.2. Verification of the ADC/DAC Controller....................50
4.1.3. Synthesis Result of the ADC/DAC Controller................50
4.2. Verification of the Template retrieval IP.................52
4.2.1. Verification of the Template Retrieval IP.................52
4.2.2. Synthesis Results of the Template Retrieval IP............54
4.3. Implementation and Verification of the Proposed SOPC
for Spoken Language Translation System....................56
4.3.1. Implementation of the proposed SOPC.......................57
4.3.2. HW/SW co-verification.....................................58
4.3.3. Experimental Result.......................................59
4.3.4. Chip Feature..............................................60

CHAPTER 5 CONCLUSIONS AND FUTURE WORKS...........................63

REFERENCES........................................................64

Appendix A Control Tables of Template Retrieval IP...............68

[1]Lavie et al., “JANUS III: speech-to-speech translation in multiple languages,” in Proc. IEEE Int. Conf. Acoustics, Speech and Signal Processing, Apr. 1997, pp. 99–102.
[2]W. Wahlster, Verbmobil: Foundations of Speech-to-Speech Translation. Berlin Heidelberg, New York: Springer-Verlag, 2000.
[3]H. Ney, S. Nießen, F. J. Och, H. Sawaf, C. Tillmann, and S. Vogel, “Algorithms for statistical translation of spoken language,” IEEE Trans. Speech and Audio Processing, vol. 8, pp. 24-36, Jan. 2000.
[4]F. Casacuberta et al., ”Speech-to-speech translation based on finite-state transducers,” in Proc. IEEE Int. Conf. Acoustics, Speech and Signal Processing, May 2001, pp. 613–616.
[5]F. Sugaya, T. Takezawa, A. Yokoo, and S. Yamamoto, “End-to-end evaluation in ATR-MATRIX: speech translation system between English and Japanese,” in Proc. 6th Eur. Conf. Speech Communication and Technology, Sep. 1999, pp. 2431–2434.
[6]P. C. Ching and H. H. Chi, “ISIS: a trilingual conversational system with learning capabilities and combined interaction and delegation dialogs,” in Proc. National Conf. Man-Machine Speech Communications, Nov. 2001, pp. 119–124.
[7]R. Isotani, K. Yamabana, S. Ando, K. Hanazawa, S. Ishikawa, T. Emori, H. Hattori, A. Okumura, and T. Watanabe, “An automatic speech translation system on PDAs for travel conversation,” in Proc. IEEE Int. Conf. Multimodal Interfaces, Oct. 2002, pp. 211–216.
[8]A. Waibel, A. Badran, A. W. Black, R. Frederking, D. Gates, A. Lavie, L. Levin, K. Lenzo, L. M. Tomokiyo, J. Reichert, T. Schultz, D. Wallace, M. Woszczyna, and J. Zhang, “Speechalator: two-way speech-to-speech translation on a consumer PDA”, in Proc. European Conf. Speech Communication and Technology, Sep. 2003, pp. 369–372.
[9]T. Watanabe, A. Okumura, S. Sakai, K. Yamabana, S. Doi, and K. Hanazawa, “An automatic interpretation system for travel conversation,” in Proc. Int. Conf. Spoken Language Processing, Sep. 2000, pp. IV-444–IV-447.
[10]J. F. Wang, B. Z. Houg, and S. C. Lin, “A study for Chinese text to Taiwanese speech system,” in Proc. Int. Conf. Research on Computational Linguistics, Aug. 1999, pp. 37–53.
[11]M. Simard, “Translation spotting for translation memories,” in Proc. HLT-NAACL Workshop on Building and Using Parallel Texts: Data Driven Machine Translation and Beyond, May 2003, pp. 65–72.
[12]J. Véronis and P. Langlais, “Evaluation of parallel text alignment systems – the ARCADE project,” in Parallel Text Processing, Dordrecht: Kluwer Academic, 2000, pp. 369–388.
[13]L. Rabiner and B. H. Juang, Fundamentals of Speech Recognition. Prentice-Hall, Inc., 1993.
[14]J. F. Wang, A. N. Suen, and C. K. Chieh, “A programmable application specific architecture for real-time speech recognition,” in Proc. of VLSI Design/CAD Symposium, Aug. 1995, pp. 261–264.
[15]H. Kalte, D. Langen, E. Vonnahme, A. Brinkmann, and U. Ruckert. “Dynamically Reconfigurable System-on-Programmable-Chip”. Heinz Nixdorf Institute, System and Circuit Technology University of Paderborn, 33102 Paderborn, Germany. In IEEE Computer society Conference, 2002.
[16]Fan-Min Li, “SOC Design for Speech to Speech Translation”, Master thesis, EE. NCKU, 2002.
[17]Steven Chou. “Altera Quartus II”. CIC teaching materials. In www.cic.edu.tw, Jan 2003.
[18]ALTERA, “Quartus II Handbook, Volume 1, Volume 2, Volume3”, Document Part No. QII5V1-1.0, http://www.altera.com, February 2004.
[19]ALTERA, “EPXA10 Development Board Hardware Reference Manual”, Document Part NO. MNL-EXPA10DEVBD-1.1, http://www.altera.com, April 2002.
[20]ALTERA, “Excalibur Devices Hardware Reference Manual”, Document Part NO. MNL-EXPA10HRM-3.1, http://www.altera.com, Nov 2002.
[21]ALTERA, “Excalibur Stripe Simulator”, Document Part No. UG-EXCFSSIM-1.5, http://www.altera.com, April 2003.
[22]ALTERA, “Excalibur Hardware Design Tutorial”, Document Part NO. A-MNL_ARMTUTORIAL-1.5, http://www.altera.com, August 2002.
[23]ALTERA, “Bus Functional Model”, Document Part NO. UG-XBUS-1.2, http://www.altera.com, July 2002.
[24]ALTERA, “Excalibur Solutions - Using the Expansion bus Interface”, Document Part NO. A-AN-143-1.0, http://www.altera.com, Oct 2002.
[25]ALTERA, “Using the interrupt controller”, Document Part NO. AN-191-1.3, http://www.altera.com, Dec 2002.
[26]ALTERA, “Simulating Excalibur Systems”, Document Part NO. AN-240-1.0, http://www.altera.com, September 2002.
[27]ALTERA, “System Development Tools for Excalibur Devices”, Document Part NO. AN-299-1.1, http://www.altera.com, June 2003.
[28]ARM, “ARM Architecture Reference Manual”, Document Part NO. ARM DDI 0100E, http://www.arm.com, Jun 2000.
[29]ARM, “ARM922T Technical Reference Manual”, Document Part NO. ARM DDI 0184A, http://www.arm.com, Sep 2000.
[30]ARM, “AMBA Specification (Rev 2.0)” ARM Document N0. ARM IHI0011A, http://www.arm.com, May 1999.
[31]ARM, “ARM Developer Suit version 1.2 AXD and armsd Debuggers Guide”, Document Part NO. ARM DUI 0066D, http://www.arm.com, November 2001.
[32]ARM, “ARM Developer Suit version 1.2 Compilers and Libraries Guide”, Document Part NO. ARM DUI 0067D, http://www.arm.com, November 2001.
[33]ARM, “Application Note 34 Writing Efficient C for ARM”, Document Part NO. ARM DAI 0034A, http://www.arm.com, January 1998.
[34]Synosys, “DesignWare AMBA On-Chip Bus Release Notes”, Synopsys, Inc. http://www.synopsys.com, December 9, 2003.
[35]Synopsys, “DesignWare DW_apb Databook”, Synopsys, INC. http://www.synopsys.com, October 20, 2003.