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研究生:楊學偉
研究生(外文):Hsueh-Wei Yang
論文名稱:基於ARM微處理器之語音翻譯可程式化系統單晶片設計
論文名稱(外文):An ARM-based SOPC Design of Spoken Language Translation System
指導教授:王駿發
指導教授(外文):Jhing-Fa Wang
學位類別:碩士
校院名稱:國立成功大學
系所名稱:電機工程學系碩博士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2004
畢業學年度:92
語文別:英文
論文頁數:71
中文關鍵詞:語音辨識語音翻譯ARM微處理器可程式化系統單晶片系統單晶片
外文關鍵詞:SOCSOPCARM processorspeech recognitionspoken language translation
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  語音翻譯是未來語音與語言技術一個重要的應用,本篇論文提出一個基於ARM微處理器的可程式化系統晶片設計應用於可攜性的語音翻譯,此可程式化系統晶片具有小面積、低成本、即時處理、高可靠度與具靈活性的特性,我們利用一個例句式模板檢索演算法來加快處理速度與節省記憶體需求量,在所提出的語音翻譯可程式化系統晶片設計中,包含了基於AMBA匯流排的可程式化系統晶片架構設計、數位/類比轉換電路設計(包含類比印刷電路板與數位控制電路矽智產)、模板檢索矽智產設計與系統中之軟體處理程序設計,並將整個設計實現於ALTERA公司的EPXA10F1020C2發展平台,在40 MHz的工作時脈下,ㄧ個100句模板的翻譯動作將會在0.5秒內完成,此系統的最大頻率可達46.22 MHz,使用的邏輯元件為19,318 (佔EPXA10全部邏輯元件的50%)。
  Spoken language translation is a prospective application of speech and language technology. This thesis presents an ARM-based system on a programmable chip (SOPC) design for a portable spoken language translation application. This SOPC is characterized by small size, low cost, real-time operation, high reliability and flexibility. We adopt the example-based template retrieval algorithm to speed up process and to reduce memory requirement. For SOPC realization of the proposed SLT system, this work designs the AMBA-based SOPC architecture, the AD/DA conversion circuit (include analog PCB and logic controller IP), the template retrieval IP and the software procedures of the SOPC. We implement the entire design with ALTERA EPXA10F1020C2 device. The translation process can be completed within 0.5 second at a 40 MHz clock frequency while the number of templates is 100. The maximum frequency is 46.22 MHz, and the usage of logic elements is 19318 (50% of the total logic elements of EPXA10 device).
中文摘要...........................................................i
ABSTRACT..........................................................ii
ACKNOWLEDGMENTS..................................................iii
LIST OF FIGURES..................................................vii
LIST OF TABLES.....................................................x

CHAPTER 1 INTRODUCTION............................................1
1.1. Introduction to Spoken Language Translation................1
1.2. Motivation.................................................3
1.3. Framework of the Proposed System...........................3
1.4. Organization of Thesis.....................................7

CHAPTER 2 THE PROPOSED SOPC ARCHITECTURE..........................8
2.1. Overview of the SOPC Development Board.....................8
2.1.1. AlteraTM ExcaliburTM EPXA10 Development Board..............8
2.1.2. ARM-based ExcaliburTM Device..............................10
2.2. Hardware/Software Partitioning............................12
2.3. Hardware Architecture of the SOPC for Spoken Language
Translation system........................................14

CHAPTER 3 HARDWARE/SOFTWARE CO-DESIGN............................16
3.1. Analog-to-Digital / Digital-to-Analog Converter...........16
3.1.1. Description of the Converter Board and the Controller.....16
3.1.2. Analog Circuit of ADC/DAC.................................19
3.1.3. Digital Circuit of the Controller.........................20
3.1.4. Timing Diagrams between Advanced High-performance Bus
and Advanced Peripheral Bus...............................22
3.2. Template Retrieval IP Design..............................23
3.2.1. Description of Template Retrieval IP......................23
3.2.2. Data Flow Projection......................................26
3.2.3. Hardware Design of the Template Retrieval IP..............29
3.2.4. The Controller Design.....................................35
3.3. Memory Allocation.........................................38
3.4. Software Procedure........................................40
3.4.1. Speech Signal Preprocessing...............................40
3.4.2. Pattern Extraction Procedure..............................42

CHAPTER 4 IMPLEMENTATION AND VERIFICATION........................48
4.1. Implementation of AD/DA Conversion Circuit................49
4.1.1. Implementation of the ADC/DAC Circuit Board...............49
4.1.2. Verification of the ADC/DAC Controller....................50
4.1.3. Synthesis Result of the ADC/DAC Controller................50
4.2. Verification of the Template retrieval IP.................52
4.2.1. Verification of the Template Retrieval IP.................52
4.2.2. Synthesis Results of the Template Retrieval IP............54
4.3. Implementation and Verification of the Proposed SOPC
for Spoken Language Translation System....................56
4.3.1. Implementation of the proposed SOPC.......................57
4.3.2. HW/SW co-verification.....................................58
4.3.3. Experimental Result.......................................59
4.3.4. Chip Feature..............................................60

CHAPTER 5 CONCLUSIONS AND FUTURE WORKS...........................63

REFERENCES........................................................64

Appendix A Control Tables of Template Retrieval IP...............68
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