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研究生:謝翠玲
研究生(外文):Tsuei-Ling Hsieh
論文名稱:ARM9架構下之嵌入式微處理器設計與測試
論文名稱(外文):Design and Test of Embedded Processors Based on ARM9 Structure
指導教授:李昆忠李昆忠引用關係
指導教授(外文):Kuen-Jong Lee
學位類別:碩士
校院名稱:國立成功大學
系所名稱:電機工程學系碩博士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2004
畢業學年度:92
語文別:英文
論文頁數:47
中文關鍵詞:微處理器測試設計
外文關鍵詞:functional testingCPUprocessortesting
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  在現今的單晶片系統技術下,我們能在單一晶片整合越來越多智產核心電路。因此,在系統中將可能用到一個或多個一般或是特殊功能的處理器。雖然處理器的使用越來越廣泛,但是由於處理器貧乏的控制性及觀察性導致測試上越來越困難。傳統上的測試方法是利用在電路中加上掃瞄鍊的方式,但此種方法可能會造成電路面積與費用的增加。除此之外,這種方法也會因此造成效能的降低。功能性的測試方法可用以解決上述的問題。在功能性測試中,測試資料將由功能性輸入腳位輸入,並由輸出觀察結果。在功能性測試中,重要的是如何產生好的測試程式。在這篇論文中,我們將展示一種產生測試程式的方法以及測試結果的一些分析。
  為了實現我們的方法,我們使用在開放核心網站上的一個ARM9處理器作為測試樣本。除了測試之外,我們還設計了一顆ARM9+的處理器作為日後分析所用。在實驗結果中我們展示我們的測試程式將可達到不錯的測試結果,而且我們也將顯示一個有系統的結果分析。
  With the evolution of SOC technology, more and more IP cores can be integrated into a single chip. As a result, more and more processors are used for either general or special purpose. Although the processors are widely used in various applications, the poor controllability and observability of processors result in the hurdle of testing. Traditional test methods mainly insert scan chain into the circuits. However, this kind of approaches usually cause the overhead of area and cost, and many seriously degrade the performance. Therefore, functional testing has been developed as an alternative. In functional testing, the test patterns are applied through the functional input pins and the responses are observed from the functional output pins, hence no modification on the processor is required. Therefore, all what matter is how to generate good test programs. In this thesis, we present a method to generate test programs with high fault coverage. The effectiveness of these programs will be extensively analyzed. An ARM9 processor, which is called nnARM from OpenCore website, is used as the benchmark. Experimental results show our test programs can achieve 93.78% fault coverage, which is superior to any previous method. However because there still exists much space to improve, we also employ both partial scan and full scan in the processor and make a comparison between these methods. Experimental results show that with a partial scan on the ALU shell of the processor, 95% fault coverage can be obtained. While the full scan design will lead to move than 99% fault coverage.
  In addition to testing, in this thesis we also design an ARM9+ processor which is more general and will be very useful for future development of functional testing methodology. This processor has been verified through several manual programs as well as a sorting program provided by the ARM Development System.
Chapter 1 INTRODUCTION1
1.1 MOTIVATION1
1.2 ARM9 PROCESSOR ARCHITECTURE AND TESTING2
1.3 ORGANIZATION OF THESIS2
Chapter 2 BACKGROUND AND PREVIOUS WORK5
2.1 CONCEPT OF FUNCTIONAL TESTING5
2.2 CONCEPT OF SCAN TESTING7
2.2.1 Scan design7
2.2.2 BIST design8
2.3 NNARM ARCHITECTURE OVERVIEW9
2.3.1 Instruction Set Overview9
2.3.2 Architecture Overview10
Chapter 3 TEST PLAN12
3.1 FUNCTIONAL TESTING12
3.1.1 Deterministic Test Program12
3.1.1.1 Register File Test13
3.1.1.2 Data Path Test14
3.1.1.3 Decoder (Addressing Mode Test)14
3.1.1.4 Forwarding Test15
3.1.2 Pseudo-Random Test Program16
3.2 SCAN TESTING18
3.2.1 Partial Scan18
3.2.2 Full Scan19
Chapter 4 TEST ARCHITECTURE IN NNARM20
4.1 TEST SYSTEM20
4.2 TEST SHELL21
4.2.1 Multiplexers22
4.2.2 Data Address Mask22
4.2.3 Test Controller23
4.2.3.1 Control the Test Procedure23
4.2.3.2 Generating Interrupt Signals23
4.2.4 MISR (Multiple-Input-Signature-Register)24
Chapter 5 SIX-STAGE ARM9+ PROCESSOR ARCHITECTURE25
5.1 INSTRUCTION SET25
5.1.1 Data Processing27
5.1.2 Multiplication28
5.1.3 Status register access28
5.1.4 Branch29
5.1.5 Load and Store29
5.1.6 Semaphore29
5.1.7 Multiple Load and Multiple Store29
5.1.8 Coprocessor30
5.1.9 SWI30
5.1.10 Undefined30
5.2 ARCHITECTURE OVERVIEW30
5.2.1 Instruction Fetch31
5.2.2 Instruction Decoder31
5.2.3 Register File32
5.2.4 Instruction Execution32
5.2.5 Memory data access33
5.2.6 Write Back33
Chapter 6 TEST ARCHITECTURE IN ARM9+34
6.1 TEST SYSTEM34
6.2 THE MODIFIED COMPONENTS35
6.2.1 Test Data Background Generator36
6.2.2 D-MUX36
6.2.3 Multiple Input Signature Register (MISR)37
Chapter 7 EXPERIMENTAL RESULTS38
7.1 FUNCTIONAL TESTING & HARDWARE SYSTEM FOR NNARM38
7.1.1 Benchmark Circuit (nnARM Core)38
7.1.2 Test Shell for nnARM39
7.2 FUNCTIONAL TESTING FOR NNARM39
7.3 SCAN TESTING FOR NNARM40
7.4 ARM9+ VERIFICATION RESULT40
7.5 ARM9+ SYNTHESIS REPORT43
Chapter 8 CONCLUSIONS AND FUTURE WORK44
8.1 CONCLUSIONS44
8.2 FUTURE WORK 44
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[11]R. S. Tupuri and J. A. Abraham, “A Novel Hierarchical Test Generation Method for Processors,” International Conference on VLSI Design, pp.540-541, January 1997.
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[13]R. S. Tupuri, A. Krishnamachary and J. A. Abraham, “Test Generation for Gigahertz Processors Using an Automatic Functional Constraint Extractor,” Design Automation Conference, pp.647-652, 1999.
[14]V. M. Vedula and J. A Abraham, “A Novel Methodology for Hierarchical Test Generation using Functional Constraint Composition,” High-Level Design Validation and Test Workshop, pp.9-14, 2000.
[15]L. Chen, S. Dey, P. Sanchez, K. Sekar and Y. Chen, “Embedded Hardware and Software Self-Testing Methodologies for Processor Cores,” Design Automation Conference, pp.625-630, 2000.
[16]F. Cormo, M. S. Reorda, G. Squillero and M. Violante, “A Genetic Algorithm-based System for Generating Test Programs for Microprocessor IP Cores,” International Conference on Tools with Artificial Intelligence, pp.195-198, 2000.
[17]A. Burdass, G. Campbell, R. Grisenthwaite, D. Gwilt, P. Harrod and R. York, “Embedded Test and Debug of Full Custom and Synthesisable Microprocessor Cores,” European Test Conference, pp.17-22, 2000.
[18]Steve Furber, “ARM system-on-chip architecture”, ADDISON-WESLEY, in Great Britain, 2000.
[19]“ARM Architecture Reference Manual”, ARM corporation.
[20]M.-C. Chen, “A Hybrid Method on Functional Testing for Embedded Process Cores,” Master Thesis, Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan, ROC, June 2003.
[21]D. A. Patterson and J. L. Hennessy, “ Computer Organization & Design: The Hardware/Software Interface”, Morgan Kaufmann Publishers, December 1997.
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