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研究生:劉昀儒
研究生(外文):Yun-Ju Liu
論文名稱:一個應用於S/PDIF音效處裡的時脈與資料回復電路
論文名稱(外文):A Clock and Data Recovery for S/PDIF Audio Application
指導教授:郭泰豪
指導教授(外文):Tai-Haur Kuo
學位類別:碩士
校院名稱:國立成功大學
系所名稱:電機工程學系碩博士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2004
畢業學年度:92
語文別:英文
論文頁數:78
中文關鍵詞:時脈與資料回復電路
外文關鍵詞:Clock and Data RecoveryCDR
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本篇論文是實現一個S/PDIF的數位音效接收器,內建一個用0.35微米雙多晶層四金屬層的CMOS製程的時脈與資料回復電路(簡稱CDR)。本電路根據S/PDIF的介面標準來對音效與數位資料做接收和粹取時脈的工作。晶片中包含線接收器和一個時脈與資料回復電路,具有回復時脈與同步信號的功能和多路傳輸音效與數位資料的能力。

此晶片的主要功能是回復音效資料並從數位的傳輸線中取得且產生低污染的時脈。從時脈與資料回復電路所產生的時脈有主時脈(MCK,256倍的取樣頻率),信號時脈(SCK,64倍的取樣頻率)和基礎頻率(FSYNC,1倍或2倍的取樣頻率)。被接收的音效資料(S/PDIF)能利用數位解碼器來轉換成I2S的音效格式。因此,本篇論文實現了一個S/PDIF的數位音效接收器,內建一個用時脈與資料回復電路。在一些應用方面像是接在光碟機輸出端的音效接收器或是接在數位電視輸出端的音效接收器,等等。

整個IC晶片的總面積是0.657mm2而其中不含Pads的總面積是 0.249mm2。此晶片的總功率消耗是33.5mW。
A S/PDIF Digital Audio Receiver with an Internal Clock and Data Recovery (CDR) circuit is implemented in 0.35um 2P4M CMOS Technology. The circuit receives audio and digital data according to the S/PDIF interface standard. The chip contains line receivers and a clock and data recovery circuit that recovers the clock and synchronization signals, and de-multiplex audio and digital data.

The primary function of the chip is to recover audio data and low jitter clocks from a digital transmission line. The clocks that can be generated by CDR are MCK (256x Fs), SCK (64x Fs), and FSYNC (Fs or 2x Fs). The recovered audio data (S/PDIF) can be transferred into I2S format by digital decoder. Thus, this thesis implements a S/PDIF Digital Audio Receiver with an Internal clock and data recovery circuit. Applications such as CD-ROM output audio receiver, Digital TV output audio receiver, etc..

The chip total area is 0.657mm2 and active area is 0.249mm2. The total power consumption is 33.5mW.
Contents

1 Introduction 1
1.1 Background ………………………………………… 1
1.2 Motivation ………………………………………… 2
1.3 Thesis Organization ……………………………… 3

2 Audio Systems 5
2.1 Introduction ……………………………………… 5
2.2 Audio Data Format ………………………………… 6
2.2.1 Bi-Phase Mark Coding ………………………… 9
2.2.2 I2S, Right Alignment, Left Alignment Format … 11
2.3 Specification for Audio Systems …………… 14
2.3.1 AES/EBU Professional Format ……………… 15
2.3.2 S/PDIF Consumer Format ……………………… 15

3 Fundamentals and Design Techniques of Clock and Data Recovery 17
3.1 General Considerations ………………………… 17
3.2 Phase Detectors for Random Data …………… 19
3.2.1 Hogge Phase Detector ……………………… 20
3.2.2 Alexander Phase Detector ………………… 22
3.2.3 Half-Rate Phase Detector ………………… 25
3.3 Frequency Detectors for Random Data ……… 30
3.4 CDR Architectures ……………………………… 33
3.4.1 Full-Rate Referenceless Architecture … 34
3.4.2 Dual-VCO Architecture …………………… 35
3.4.3 Dual-Loop Architecture with External Referenc … 37

4 Circuits implementation of Clock and Data Recovery and Digital Decoder 40
4.1 Introduction ……………………………………… 40
4.2 Design of Clock and Data Recovery ………… 41
4.2.1 Phase Detector ……………………………… 42
4.2.2 Frequency Detector ………………………… 48
4.2.3 Charge Pump and Loop Filter ……………… 49
4.2.4 Voltage-Controlled Oscillator …………… 51
4.2.4.1 Digital Logic Control Circuit ( Coarse Tune ) ……………………… 57
4.2.4.2 Replica Bias Voltage Control Circuit ( Fine Tune ) ……………… 60
4.2.5 Differential to Single-Ended Circuit …… 64
4.2.6 9-Bits Synchronous Divider ………………… 66
4.2.7 Phase-Locked Loop and Frequency-Locked Loop … 68
4.2.8 CDR Layout ……………………………………… 70

5 Verifications and Measurements 71

6 Conclusions and Future Works 73

References 75
References

[1] D.G. Goff, Fiber Optic Reference Guide, Boston:Focal Press, 1999

[2] J. Savoj and B. Razavi, “ A 10-Gb/s CMOS Clock and Data Recovery Circuit,” Symp. on VLSI Circuits Dig. of Tech. Papers, pp. 136-139, June 2000.

[3] M. M. Green et al., “ OC-192 Transmitter in Standard 0.18um CMOS,” ISSCC Dig. of Tech. Papers, pp. 186-187, Feb. 2002.

[4] J. Cao et al., “ OC-192 Receiver in Standard 0.18um CMOS,” ISSCC Dig. of Tech. Papers, pp. 187-188, Feb. 2002.

[5] N. M. Nguyen and R. G. Meyer, “Start-up and Frequency Stability in High Frequency Oscillators,” IEEE Journal of Solid-State Circuits, vol. 27, pp. 810-820, May 1992.

[6] I. A. Young, J. K. Greason, and K. L. Wang, ”A Clock Generator with 5 to 110 MHz of Lock Range for Microprocessors,” IEEE Journal of Solid-State
Circuits, vol. SC-27, pp.1599-1607, Nov. 1992.

[7] B. Lai and R. C. Walker, “A Monolithic 622 Mb/sec Clock Extraction and Data Retiming Circuit,” ISSCC Dig. Tech. Papers, pp. 144-145, Feb. 1991.

[8] S. K. Enam and A. A. Abidi, “NMOS ICs for Clock and Data Regeneration in Gigabit-per-Second Optical-Fiber Receivers,” IEEE Journal of Solid-State Circuits, vol. SC-27, pp.1763-1774, Dec. 1992.

[9] C. R. Hogge, “A Self-Correcting Clock Recovery Circuits,” IEEE J. Lightwave Tech., vol. 3, pp1312-1314, Dec. 1985.

[10] S. B. Anand and B. Razavi, “A 2.75-Gb/s CMOS Clock and Data Recovery Circuits with Broad Capture Range, “ ISSCC Dig. of Tech. Papers, pp. 214-215, Feb. 2001.

[11] L. DeVito et al., “A 52 MHz and 155 MHz Clock Recovery PLL,“ ISSCC Dig. of Tech. Papers, pp. 142-143, Feb. 1991.

[12] L. DeVito, “A Versatile Clock Recovery Architecture and Monolithic Implementation,” in Monolithic Phase-Locked Loops and Clock Recovery
Circuits, B. Razavi, Ed., New York: IEEE Press, 1996.

[13] J. D. H. Alexander, “Clock Recovery from Random Binary Data,” Electronics Letters, vol. 11, pp. 541-542, Oct. 1975.

[14] R.C. Walker, et al., “A 1.5 Gb/s Link Interface Chipset for Computer Data Transmission,” IEEE J. of Selected Areas in Communications, vol. 9, pp. 698-703, June 1991.

[15] Y. M. Greshishchev, et al., “A Fully Integrated SiGe Receiver IC for 10-Gb/s Data Rate,” IEEE Journal of Solid-State Circuits, vol.35, pp. 1949-1957, Dec. 2000.

[16] J. Savoj and B. Razavi, “A 10-Gb/s CMOS Clock and Data Recovery Circuit with a Half-Rate Linear Phase Detector,” IEEE Journal of Solid-State Circuits, vol. 36, pp. 761-768, May 2001.

[17] F. M. Gardner, “Properties of Frequency Difference Detectors,” IEEE Trans. Comm., vol. 33, pp. 131-138, Feb. 1985.

[18] A. Pottbacker, U. Langmann, and H. U. Schreiber,” A Si Bipolar Phase and Frequency Detector for Clock Extraction up to 8 Gb/s,” IEEE Journal of Solid-State Circuits, vol. 27, pp. 1747-1751, Dec. 1992.

[19] D. G. Messerschmitt, “Frequency Detectors for PLL Acquisition in Timing and Carrier Recovery,” IEEE Trans. Comm., vol. 27, pp. 1288-1295, Sept.1979.

[20] J. Savoj and B. Razavi, “A 10-Gb/s CMOS Clock and Data Recovery Circuit with Frequency Detectors,” ISSCC Dig. of Tech. Papers, pp. 78-79,
Feb. 2001.

[21] J. C. Scheytt, G. Hanke, and U. Langmann, “A 0.155, 0.622, and 2.488 Gb/s Automatic Bit Rate Selecting Clock and Data Recovery IC for Bit Rate
Transparent SDH Systems,” ISSCC Dig. of Tech. Papers, pp. 348-349, Feb. 1999.

[22] P. Trischitta and E. Varma, Jitter in Digital Transmission Systems, Norwood, MA: Artech House, 1989.

[23] F. Herzel and B. Razavi, “A Study of Oscillator Jitter Due to Supply and Substrate Noise,” IEEE Trans. Circuits and Systems, Part II, vol. 46, pp. 56-62, Jan. 1999.

[24] J. A. McNeill, “Jitter in Ring Oscillators,” IEEE Journal Solid-State Circuits, vol. 32, pp. 870-879, June 1997.

[25] J. G. Maneatis, “Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques,” IEEE Journal of Solid-State Circuits, vol. 31, pp.1723-1732, Nov. 1996.

[26] J. F. Parker and D. Ray, “A 1.6-GHz CMOS PLL with On-Chip Loop Filter,” IEEE Journal of Solid-State Circuits, vol. 33, pp. 337-343, March 1998.

[27] B. Kim, D. Helman, and P. R. Gray, “A 30 MHz Hybrid Analog/Digital Clock Recovery Circuit in 2 um CMOS,” IEEE Journal of Solid-State Circuits, vol.25, pp. 1385-1394, Dec. 1990.

[28] O. T.-C. Chen and R. R.-B. Sheen, “A Power-Efficient Wide-Range Phase-Locked Loop,” IEEE Journal of Solid-State Circuits, vol.37, pp. 51-62, Jan. 2002.

[29] P. Larsson, “A 2-1600 MHz CMOS Clock Recovery PLL with Low-VDD Capability,” IEEE Journal of Solid-State Circuits, vol. 34, pp. 1951-1960, Dec. 1999.

[30] C.-H. Park and B. Kim, “A low-noise 900 MHz VCO in 0.6 um CMOS,” IEEE Journal Solid-State Circuits, vol. 34, pp. 1586–1591, May 1999.

[31] J. Lee and B. Kim, “A 250 MHz low jitter adaptive bandwidth PLL,” in Proc. IEEE Int. Solid-State Circuits Conf., 1999, pp. 346–347.

[32] A. Hajimiri and T. H. Lee, “A general theory of phase noise in electrical oscillators,” IEEE J. Solid-State Circuits, vol. 33, pp. 179–195, Feb. 1998.

[33] K. Iravani, F. Saleh, D. Lee, P. Fung, P. Ta, and G. Miller, “Clock and data recovery for 1.25 Gb/s Ethernet transceiver in 0.35 um CMOS,” in Proc. Custom Integrated Circuits Conf., 1999, pp. 261–264.

[34] V. V. Kaenel, D. Aebisher, C. Piguet, and E. Dijkstra, “A 320 MHz, 1.5 mW at 1.35 V CMOS PLL for microprocessor clock generation,” in Proc. IEEE Int. Solid-State Circuits Conf., 1996, pp. 132–133.
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