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研究生:溫世存
研究生(外文):shi-cun wen
論文名稱:應用於Gb/s之低電壓差動訊號傳輸介面的設計與實現
論文名稱(外文):Design and Implementation for Gb/s LVDS I/O Application
指導教授:盧志文盧志文引用關係
指導教授(外文):Chih-Wen Lu
學位類別:碩士
校院名稱:國立暨南國際大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2004
畢業學年度:92
語文別:中文
論文頁數:89
中文關鍵詞:低電壓差動訊號傳輸器接收器鎖相迴路
外文關鍵詞:Low voltage differential signaltransmitterreceiverPLL
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近幾年來,由於處理器運算速度越來越快,單位時間處理的資料量也日益增多,因此在電腦週邊設備資料的傳輸,以及各式積體電路產品的應用,都必須靠一個能大量傳送和接收資料量的介面電路來完成,這樣使得輸入/輸出介面就扮演了一個很重要的角色。為了完成高速度與低功率的傳輸要求,利用低電壓差動訊號輸出(low voltage differential signal, LVDS)標準所定義的傳輸方式來設計輸入輸出介面。
本論文研究的方向主要是利用低電壓差動訊號輸出(LVDS)技術來設計操作於2Gb/s的低功率傳送器與接收器,另外也介紹用來測試傳送器與接收器的鎖相迴路。
吾人所設計之低電壓差動訊號(LVDS)傳送器與接收器是以HSPICE模擬,並以台積電提供的TSMC 0.35μm 2P4M35 CMOS製程進行設計與下線製作。模擬結果顯示傳輸器與接收器的傳輸速度可達到2Gb/s。傳送器的功率消耗為21mW,第一個接收器功率消耗為15mW,第二個接收器功率消耗為9mW。
In recent year, the operation speed of processor becomes faster and faster, and could deal with huger data in unit time. Therefore, it needs a giga-bit transceiver interface circuit for the transmission between peripheral equipments of computer, and application at kinds of manufactures in life, Impel I/O interface plays an important role. Low voltage differential signal (LVDS) I/O standard used for data transmission can fulfill the requirements of high speed and low power.
The research of this thesis mainly utilizes low voltage differential signal technology to design 2Gb/s and low power is transmitter and receiver, A phase locked loop for testing the transceiver is also introduced.
HSPICE is used to verify functions of LVDS transmitter and receiver.
Then the circuits are realized by using TSMC 0.35μm 2p4m35 CMOS process provided by Chip Implementation Center. simulate result transmitter and receiver, The chip can operate functionally at 2Gb/s. Transmitter power consumption is 21mW, power consumption of the first receiver is 15mW, power consumption of the second receiver is 9mW.
中文摘要……………………………………………………………….Ⅰ
英文摘要……………………………………………………………….Ⅱ
誌謝…………………………………………………………………... Ⅲ
目錄 ...…………………………………………………………………IV
圖目錄…………………………………………………………………VII
表目錄………………………………………………………………….XI
第一章 緒論 …………………………………………………………..1
1.1動機 .……………………………………………………...1
1.2 研究背景 .………………………………………………..2
1.3 論文架構 ………………………………………….……..3
第二章 低電壓差動訊號(LVDS)的規格與架構……………………...4 2.1低電壓差動訊號之規格…………………..........................5
2.1.1 低電壓差動訊號……………………………………5
2.1.2 低電壓差動擺幅…………........................................6
2.1.3 低電壓差動訊號的優點……………………………6 2.1.4 低電壓差動訊號的規格…………………................6
2.2低電壓差動訊號之介面架構與原理……..........................7
2.3高速電路設計之考量……………………………………..8
2.3.1反射(Reflect)………………………………….........8
2.3.2串音(Crosstalk)………………………....................10
2.3.3接地彈跳(Ground bounce)………………………...11
第三章 2G/bs與低功率的傳輸器設計和實現……………………….13
3.1介紹….................................................................................14
3.2電路設計…………………………………….....................16
3.2.1傳輸器的電路………………………………...........16
3.2.2 終端電阻…………………………….....................18
3.3模擬…………………………............................................19
第四章 2G/bs與低功率的接收器設計和實現………………...........23
4.1介紹……………………………………………………....23
4.2電路設計………………………………………………....24
4.2.1接收器1……………………………………............24
4.2.2接收器2…………………………………................27
4.2.3終端電阻……………………………………...........32
4.3模擬………………………………………..........................32
4.4測試考量..............................................................................35
第五章 鎖相迴路(PLL)的設計………………………………………38
5.1鎖相迴路(PLL)的介紹與設計……………………………39
5.2相位頻率檢測器(Phase/Frequency Detector, PFD )….......40
5.2.1相位頻率檢測器的觀念………...................................41
5.2.2相位頻率檢測器電路……….......................................43
5.3電荷幫浦(Charge pump)與迴路濾波器(Loop fliter) …….44
5.3.1電荷幫浦與迴路濾波器的基本觀念...........................44
5.3.2電荷幫浦與迴路濾波器電路...................................... 48
5.4電壓控振盪器(Voltage-controlled oscillator)…………….51
5.4.1電壓控振盪器的基本觀念...........................................52
5.4.2電壓控制振盪器電路...................................................55
5.5除頻器(Divider)…………………………….......................57
5.5.1除頻器電路的基本觀念...............................................57
5.5.2除頻器電路...................................................................58
5.6模擬與量測結果………………………………………......61
5.6.1鎖相迴路的模擬...........................................................61
5.6.2鎖相迴路的量測...........................................................66
第六章 結論 ………………………………………………………....72
參考文獻................................................................................................74
圖 目 錄
圖1-1 各式各樣的輸入/輸出介面規格…………………………….......2
圖2-1 低電壓差動訊號(LVDS)典型的介面架構………………….......8
圖2-2 接收器輸入臨限電壓的限制………………………………....…8
圖2-3 傳輸線的等效模型…………………………………………........9
圖2-4 模擬終端電阻匹配/不匹配[3]…………………………………10
圖2-5 在兩條平行線之間互感和寄生電容引起串音……………..…11
圖2-6 晶片介面上的電子模型……………………………………..…12
圖3-1 典型的傳輸器模型…………………………………………......14
(a) 當電晶體M1和M3導通時傳輸器的操作……………..….15
(b) 當電晶體M2和M4導通時傳輸器的操作…………...……15
圖3-2 吾人所設計的傳輸器..................................................................17
圖3-3 終端電阻的方法……………………………………………......19
圖3-4 傳輸器經由0.3mm長傳輸線的差動輸出(Voa、Vob)圖….....20
圖3-5 傳輸器經由0.3mm長傳輸線的差動輸出訊號(Voa)的..........
(eye diagram)……………………………………………………20
圖3-6 輸入訊號為sin波的傳輸器輸出波形…………………………21
圖3-7 輸入訊號為sin波的傳輸器輸出眼圖(eye diagram)……….....21
圖4-1 基本的接收器(receiver)模型......................................................24
圖4-2 典型的LVDS接收器(receiver)圖……………………………..24
圖4-3 吾人所設計的LVDS接收器(receiver)電路…………………..26
圖4-4 N型差動輸入和P型差動輸入都導通時Vcom與電流(I)....
的轉移曲線..................................................................................27
圖4-5 (a)基本的電流鏡所形成的正回授電路 (b)N型和P型的轉移
曲線.............................................................................................28
圖4-6 加入一個開關形成的正回授電路…………………………….28
圖4-7 吾人所設計的自給偏壓差動比較器………………………….29
圖4-8 吾人所設計的自給偏壓差動比較器………………………….30
圖4-9 隨著共模輸入電壓增加或減少的電流量…………………….30
圖4-10 吾人所設計的LVDS接收器(receiver)電路…………………31
圖4-11 共模電壓為1.65v接收器1的輸出波形…………………….32
圖4-12 輸入訊號為sin波接收器1輸出眼圖(eye diagram)………...33
圖4-13 共模電壓為2.4接收器2的輸出波形……………………….33
圖4-14 輸入訊號為sin波的接收器2輸出眼圖(eye diagram)……...34
圖4-15 接收器2的消耗功率…………………………………………34
圖4-16 接收器1 Vcom與電流模擬圖...……………………………..35
圖4-17 LVDS1的晶片佈局圖...……………………………...............36
圖4-18 LVDS2的晶片佈局圖...……………………………...............37
圖5-1 鎖相迴路(PLL)簡單之方塊圖..................................................39
圖5-2 吾人所設計之鎖相迴路(PLL)方塊圖......................................40
圖5-3 相位頻率檢測器(PFD)的方塊圖..............................................41
圖5-4 傳統三態相位頻率檢測器........................................................41
圖5-5 頻率檢測器的輸入/輸出關係...................................................42
圖5-6 相位頻率檢測器之狀態圖...........................................................43
圖5-7 (a) D型正反器 (b)相位頻率檢測器之架構圖..........................44
圖5-8 電荷幫浦基本模型....................................................................45
圖5-9 電荷幫浦和相位頻率檢測器的轉移曲線................................46
圖5-10 增加一個電阻到電荷幫浦.........................................................46
圖5-11 電荷幫浦有二階迴路濾波器的簡單模型............................... 47
圖5-12 電荷幫浦型式:開關在汲極..........................................................48
圖5-13 電荷幫浦有單增益(unit gain)緩充放大器之電路圖..............49
圖5-14 單增益(unity gain)緩衝放大器................................................50
圖5-15 單端轉雙端電路.......................................................................50
圖5-16 電荷幫浦粗調電路...................................................................51
圖5-17 傳統的環路振盪器架構...........................................................52
圖5-18 差動對構成的延遲級...............................................................53
圖5-19 為一個四級串接的雙端延遲級...............................................54
圖5-20 電壓控制振盪器(VCO)定義....................................................55
圖5-21 差動負載延遲單元電路...........................................................56
圖5-22 四級環形振盪器的結構圖....................................................57
圖5-23 雙模數前置除頻器電路...........................................................58
圖5-24 除4/5 同步除頻電路...............................................................59
圖5-25 除4/5同步除頻電路的分析圖................................................60
圖5-26 TSPC D型正反器.....................................................................61
圖5-27 外部輸入頻率超前內部產生頻率...........................................62
圖5-28 外部輸入頻率落後內部產生頻率...........................................62
圖5-29 外部輸入頻率相同內部產生頻率...........................................63
圖5-30 電荷幫浦與迴路濾波器的充電...............................................63
圖5-31 電壓控制振盪器當Vcont=0v時,輸出頻率為1.1GHz.......64
圖5-32 電壓控制振盪器當Vcont=3.3v時,輸出頻率為786MHz...64
圖5-33 Mode=0 除32之電路模擬結果............................................65
圖5-34 Mode=1 除33之電路模擬結果............................................65
圖5-35 鎖相迴路頻率鎖在900MHz................................................ 66
圖5-36 輸入訊號20MHz下之輸出波形.............................................67
圖5-37 輸入訊號20MHz下之輸入波形=輸出波形...........................67
圖5-38 輸入訊號15MHz下之輸出波形.............................................68
圖5-39 輸入訊號27MHz下之輸出波形.............................................69
圖5-40 輸入訊號27MHz下之jitter輸出波形....................................69
圖5-41 鎖相迴路(PLL)晶片佈局圖......................................................70 表 目 錄
表2-1 目前一些低電壓差動訊號(LVDS)的應用.................................. 5
表2-2 低電壓差動訊號(LVDS)傳輸器與接收器的電子規格...............7
表3-1 傳輸器(transmitter)的規格..........................................................16
表3-2 傳輸器(transmitter)模擬特性......................................................22
表4-1 接收器(receiver)的規格............................................................. 25
表4-2 接收器(receiver)模擬特性......................................................... 36
表5-1 PLL模擬特性..............................................................................71
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