(3.236.122.9) 您好!臺灣時間:2021/05/09 07:30
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果

詳目顯示:::

: 
twitterline
研究生:徐國鈞
研究生(外文):Kuo-Chun Hsu
論文名稱:具有基體觸發技術之矽控整流器及其在積體電路晶片靜電放電防護上之應用
論文名稱(外文):SILICON-CONTROLLED RECTIFIER WITH SUBSTRATE-TRIGGERED TECHNIQUE FOR ON-CHIP ESD PROTECTION IN CMOS INTEGRATED CIRCUITS
指導教授:柯明道柯明道引用關係
指導教授(外文):Ming-Dou Ker
學位類別:博士
校院名稱:國立交通大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2003
畢業學年度:92
語文別:中文
論文頁數:163
中文關鍵詞:靜電放電防護矽控整流器基體觸發技術
外文關鍵詞:ESD protectionsilicon-controlled rectifiersubstrate-triggered technique
相關次數:
  • 被引用被引用:0
  • 點閱點閱:584
  • 評分評分:系統版面圖檔系統版面圖檔系統版面圖檔系統版面圖檔系統版面圖檔
  • 下載下載:123
  • 收藏至我的研究室書目清單書目收藏:0
在眾多的靜電放電(Electrostatic Discharge, ESD)防護元件中[如:二極體(Diode)、矽控整流器(SCR)、雙載子電晶體(BJT)、金氧半場效電晶體(MOSFET)或者是場氧化層電晶體(Field Oxide Device, FOD)],矽控整流器在互補式金氧半導體(CMOS)製程技術中,具有最高的靜電放電防護能力,應用在晶片上當靜電放電防護元件也有一段很長的時間。矽控整流器(SCR)基本特性是由電流觸發而導通的元件,所以當有一電流施加於矽控整流器的基體時,矽控整流器可以很快地經由正回授再生機制(Positive-Feedback Regeneration Mechanism)觸發進入閉鎖狀態,而不需透過原本的纍增崩潰機制(Avalanche Breakdown Mechanism)。本論文深入研究矽控整流器與電流觸發的基本關係,利用電流觸發的概念並進一步設計出相關的控制電路,並實際應用在積體電路晶片上之靜電放電防護電路。
在本論文中,首先提出具有互補電路型式的基體觸發矽控整流器,用來排放焊墊到VDD或VSS電源腳位的靜電放電電流。此新型的互補式基體觸發矽控整流器具有以下優點: 可調整的切換電壓(Switching Voltage)、低持有電壓(Holding Voltage)、較快的導通速度(Turn-on Speed)、以及製程步驟完全相容於一般互補式金氧半導體的製程,不需增加額外的光罩如遮蔽金屬矽化物光罩(Silicide-Blocking Mask)和離子佈植(ESD Implantation)光罩。在0.25微米全金屬矽化的互補式金氧半導體製程中,當基體觸發電流由零增加到8 mA時,基體觸發矽控整流器的切換電壓會由原本高達22 V的電壓準位降到只有1.85 V,非常接近其持有電壓(約1.35 V)。而且,當觸發脈衝電壓的準位由1.5 V增加到4 V時,基體觸發矽控整流器的導通時間(Turn-on Time)可由27.4 ns縮短到只有7.8 ns,具有明顯增進導通速度的效果。
基體觸發矽控整流器在本論文實際製作中具有的主動面積(Active Area)只有20微米×20微米的大小,這麼小的佈局面積使得基體觸發矽控整流器在靜電放電防護電路設計中可以被堆疊以避免暫態過程所引發的閉鎖效應(Transient-Induced Latchup Issue)。對於VDD為2.5 V的0.25微米全金屬矽化的互補式金氧半積體電路應用而言,具有兩個基體觸發矽控整流器堆疊結構的靜電放電防護電路,其箝制電壓約為3.2 V,可免於閉鎖效應的危險,且仍可承受大於8 kV的人體放電模式(Human-Body-Model, HBM)及700 V的機械放電模式(Machine-Model, MM)的靜電放電耐受能力。此外,基體觸發矽控整流器的整體持有電壓也可藉由疊接二極體串來達到線性的增加。由互補式基體觸發矽控整流器搭配兩個二極體所設計的靜電放電防護電路,不具有閉鎖效應的疑慮,並可應用在輸出輸入焊墊(I/O Pads) 及VDD/VSS 電源焊墊使用之靜電放電防護電路,在0.25微米全金屬矽化的互補式金氧半導體製程中也實際被製作,在很小的佈局面積下具有7.25 kV的人體放電模式及500 V的機械放電模式的靜電放電耐受能力。
導通效率一直是矽控整流器作為晶片上靜電放電防護電路的主要隱憂,特別是在未來奈米製程中具有超薄閘氧化層的互補式金氧半導體製程。也由於矽控整流器的元件結構中,包含了一橫向的NPN及一縱向的PNP雙載子電晶體,於是本論文另外提出了創新的雙觸發技術,同時觸發NPN和PNP電晶體,更能增快矽控整流器的導通速度,用作於晶片上的靜電放電防護電路,能更有效地保護在未來奈米互補式金氧半導製程中的超薄閘氧化層。從0.25微米互補式金氧半製程中的實驗結果得知,具有20微米×20微米佈局面積的雙觸發矽控整流器,其切換電壓和導通時間均會因雙觸發技術而更有效地降低。雙觸發矽控整流器的切換電壓,在N井觸發電流為-3 mA之下,會進一步地由21 V降低至1.5 V,當基體觸發電流由0 mA增加至3 mA時。在P型觸發端施加固定的一1.5 V正的脈衝電壓,且施加在N型觸發端負電壓脈衝的絕對脈衝高度由0 V增加到5 V的條件下,雙觸發矽控整流器的導通時間會由37.6 ns大幅縮短至11.8 ns。
本論文另外也提出了一種帶有基體觸發技術和假閘極阻隔結構的矽控整流器用來改善矽控整流器的導通速度,用於晶片上的靜電放電防護電路,可為較薄的閘氧化層提供更有效的防護。這種具有假閘極結構的矽控整流器其製程是完全相容於一般互補式金氧半導體的製程,不需增加額外的光罩及製程步驟。從閘氧化層厚度為50埃的0.25微米互補式金氧半製程中的實驗結果得知,和一般具有淺溝槽隔離(Shallow Trench Isolation, STI)結構的矽控整流器相比,具有假閘極結構的基體觸發矽控整流器其切換電壓、導通速度、導通電阻(Turn-on Resistance)和元件充電放電模式(Charged-Device-Model, CDM)的靜電放電耐受能力均有顯著的改善。當施加於P型觸發端的基體觸發電流由0 mA增加至6 mA時,具有淺溝槽隔離結構的矽控整流器其切換電壓會由22 V降低至7 V,但具有假閘極結構的矽控整流器其切換電壓卻會由18 V大大地降低至3 V。
為了能快速地將靜電放電能量排放及有效率地保護超薄閘氧化層,本論文另外提出了一種新型的原生性N型金氧半電晶體觸發矽控整流器(Native-NMOS-Triggered SCR, NANSCR),作為晶片上的靜電放電防護。在靜電放電發生的情況下,原生性N型金氧半電晶體(Native NMOS)是一已導通的元件,故可以快速地引導靜電放電電流去觸發矽控整流器進入閉鎖狀態,最後,靜電放電電流便可透過導通的原生性N型金氧半電晶體觸發矽控整流器排放掉。從供應電壓為1.2 V的0.13微米互補式金氧半製程中的實驗結果得知,和傳統的低壓觸發矽控整流器(Low-Voltage Triggering SCR, LVTSCR)相比,原生性N型金氧半電晶體觸發矽控整流器的切換電壓、持有電壓、導通電阻、導通速度和元件充電放電模式的靜電放電耐受能力均有明顯的改善,更能保護超薄閘氧化層對抗靜電放電的應力(ESD Stress)。所提出的原生性N型金氧半電晶體觸發矽控整流器可被運用在輸入、輸出和電源線間的靜電放電防護電路且可免於閉鎖效應的危險。利用所提出的原生性N型金氧半電晶體觸發矽控整流器設計而成的全晶片靜電放電防護架構(Whole-Chip ESD Protection Scheme),也已經藉有針腳對針腳(Pin-to-Pin) 靜電放電測試的數據去驗證其保護效能。對於具有多電源準位的超大型互補式金氧半積體電路而言,所提出具有原生性N型金氧半電晶體觸發矽控整流器和靜電放電路徑(ESD Path)的全晶片靜電放電防護架構,是一種可以快速地排放所有靜電放電應力和有效保護內部電路的創新解決方案。
在本博士論文中,共計有五種利用基體觸發技術所設計出的矽控整流器元件,每一種元件之效能均已在實際晶片上成功驗證,並有相對應的國際期刊論文發表。本論文所研發之基體觸發矽控整流器及其相關電路設計,非常適合應用在深次微米以及未來奈米半導體製程所製作的積體電路晶片上,以有效提昇積體電路對靜電放電的防護能力。

With the highest electrostatic discharge (ESD) robustness in the smallest layout area, the silicon-controlled rectifier (SCR) device had been used in the on-chip ESD protection circuits for a long time among various ESD protection devices (such as the diode, SCR, BJT, MOS, or field oxide device) in CMOS technologies. The turn-on mechanism of a SCR device is essentially a current triggering event. While a current is applied to the base or substrate of the SCR device, it can be quickly triggered on into its latching state through the positive-feedback regeneration mechanism without involving the original avalanche breakdown mechanism. In this thesis, the dependence of the device characteristics of SCR on the triggering current is investigated in details. Then, based on the current triggering mechanism of SCR device, the corresponding ESD detection circuits are proposed to generate the triggering currents. Finally, the on-chip ESD protection circuit with the SCR devices and current-triggering circuits are realized to protect the CMOS ICs.
First, a complementary circuit style with the substrate-triggered SCR (STSCR) devices is designed to discharge both of the pad-to-VSS and pad-to-VDD ESD stresses. The novel complementary STSCR devices have the advantages of controllable switching voltage, lower holding voltage, faster turn-on speed, and fully process-compatible to general CMOS processes without extra process modification such as the silicide-blocking mask and ESD implantation. The switching voltage of the fabricated STSCR device can be reduced from ~22 to only 1.85 V, which almost equals to the holding voltage (~1.35 V) of the STSCR, when the substrate-triggered current is increased to 8 mA in a 0.25-µm fully salicided CMOS process. The turn-on time of the STSCR device can be reduced from 27.4 to 7.8 ns, while the pulse height of the triggering voltage pulse is increased from 1.5 to 4 V.
The STSCR device with a small active area of only 20 µm×20 µm can be stacked in the ESD protection circuits to avoid the transient-induced latch-up issue. For the IC application with VDD of 2.5 V, the ESD protection circuit designed with two STSCR devices in stacked configuration has a clamp voltage of ~3.2 V, free from latchup issue, and the human-body-model (HBM) (machine-model (MM)) ESD level of > 8 kV (700 V) in a 0.25-µm fully salicided CMOS process. In addition, the total holding voltage of the STSCR device can be linearly increased by adding the stacked diode string. The on-chip latchup-free ESD protection circuits designed with the proposed complementary STSCR devices and two stacked diode string for the I/O pads and power pad have been successfully verified in a 0.25-µm salicided CMOS process with the HBM (MM) ESD level of ~7.25 kV (500 V) in a small layout area.
Turn-on efficiency is the main concern for SCR devices used as on-chip ESD protection circuit, especially in future nanoscale CMOS processes with ultra-thinn gate oxide. The SCR device consists of a lateral NPN and a vertical PNP bipolar transistors, which is inherent in the CMOS processes. In this thesis, a novel double-triggered technique, used to synchronously trigger the NPN and PNP transistors in the SCR structure, is also proposed to further improve the turn-on speed of SCR devices for using in on-chip ESD protection circuit to effectively protect the much thinner gate oxide in nanoscale CMOS processes. From the experimental results in a 0.25-µm salicided CMOS process, the switching voltage and turn-on time of such double-triggered SCR (DTSCR) device, which is drawn as 20 µm×20 µm, has been confirmed to be reduced more efficiently by this double-triggered technique. The switching voltage of DTSCR under the N-well triggered current of -3 mA is further reduced from ~21 to ~1.5 V, when the substrate-triggered current is increased from 0 to 2 mA. Under the positive voltage pulse of 1.5 V at p-trigger node, the turn-on time of DTSCR can be reduced from 37.6 to 11.8 ns, while the absolute pulse height of negative voltage pulse applied to the n-trigger node is increased from 0 to 5 V.
A novel dummy-gate-blocking SCR device with substrate-triggered technique is also proposed to improve the turn-on speed of SCR device for using in the on-chip ESD protection circuit to effectively protect the much thinner gate oxide. The fabrication of the proposed SCR device with dummy-gate structure is fully process-compatible to general CMOS process, without using extra mask layer or increasing process step. From the experimental results in a 0.25-m CMOS process with the gate-oxide thickness of ~50 Å, the switching voltage, turn-on speed, turn-on resistance, and charged-device-model (CDM) ESD levels of the SCR device with dummy-gate structure have been greatly improved, as compared to the normal SCR with shallow trench isolation (STI) structure. When the substrate-triggered current applied at the p-trigger node is increased from 0 to 6 mA, the switching voltage of STSCR with STI is reduced from ~22 to ~7 V, whereas that of STSCR with dummy-gate structure is greatly reduced from ~18 to ~3 V.
In order to quickly discharge the ESD energy and to efficiently protect the ultra-thin gate oxide, a novel native-NMOS-triggered SCR (NANSCR) is proposed for on-chip ESD protection. Native NMOS is an already-on device under ESD events, so it can quickly conduct some ESD current to trigger SCR into latching state. Then, ESD current can be quickly discharged through the turned-on NANSCR device. From the experimental results in a 0.13-m CMOS process with voltage supply of 1.2 V, the switching voltage, holding voltage, turn-on resistance, turn-on speed, and CDM ESD level of NANSCR can be greatly improved to protect the ultra-thin gate oxide against ESD stresses, as compared with the traditional low-voltage triggering SCR (LVTSCR). The proposed NANSCR can be designed for the input, output, and power-rail ESD protection circuits without latchup danger. A new whole-chip ESD protection scheme realized with the proposed NANSCR devices is also demonstrated with the consideration of pin-to-pin ESD zapping. For ultra large-scale CMOS ICs with multiple power pins, the proposed whole-chip ESD protection scheme with NANSCR and ESD path is an overall solution to quickly discharge all kinds of ESD stresses and to provide efficient protection for the internal circuits.
In summary, there are totally 5 different designs on substrate-triggered SCR devices developed in this thesis. Each of the substrate-triggered SCR devices and its corresponding circuit for ESD protection have been successfully verified in the testchips and also published in the International Journals or Transactions. The developed substrate-triggered SCR devices are highly useful for on-chip ESD protection in the sub-quarter-micron CMOS integrated circuits without process modification.

ABSTRACT (CHINESE)
ABSTRACT (ENGLISH)
ACKNOWLEDGEMENTS
CONTENTS
TABLE CAPTIONS
FIGURE CAPTIONS
CHAPTER 1 INTRODUCTION
1.1 BACKGROUND
1.2 TURN-ON MECHANISM OF SCR DEVICE
1.3 SCR-BASED DEVICES FOR CMOS ON-CHIP ESD PROTECTION
1.4 SCR LATCHUP ENGINEERING
1.5 THESIS ORGANIZATION
TABLES
FIGURES
CHAPTER 2 DEVICE CHARACTERISTICS OF SUBSTRATE-TRIGGERED SCR
2.1 SUBSTRATE-TRIGGERED SCR (STSCR) DEVICE
2.2 ON-CHIP ESD PROTECTION CIRCUITS WITH STSCR DEVICES
2.2.1 ESD Protection Circuit for the Input/Output Pads
2.2.2 ESD Clamp Circuit between the Power Rails
2.2.3 Simulation Results
2.3 EXPERIMENTAL RESULTS
2.4 SUMMARY
TABLES
FIGURES
CHAPTER 3 DESIGN TECHNIQUE AND OPERATING PRINCIPLE OF ESD PROTECTION DESIGN WITH COMPLEMENTARY SUBSTRATE-TRIGGERED SCR DEVICES
3.1 COMPLEMENTARY SUBSTRATE-TRIGGERED SCR DEVICES
3.1.1 Device Structure
3.1.2 I-V Characteristics of the STSCR Devices
3.2 ON-CHIP ESD PROTECTION CIRCUITS WITH COMPLEMENTARY STSCR DEVICES
3.2.1 ESD Protection Circuit for the Input/Output Pads
3.2.2 ESD Clamp Circuit between the Power Rails
3.3 EXPERIMENTAL RESULTS
3.3.1 ESD Robustness
3.3.2 Turn-On Verification
3.4 SUMMARY
FIGURES
CHAPTER 4 SCR DEVICE WITH DOUBLE-TRIGGERED TECHNIQUE FOR EFFECTIVE ON-CHIP ESD PROTECTION
4.1 DOUBLE-TRIGGERED SCR (DTSCR) DEVICE
4.1.1 Device Structure
4.1.2 Device I-V Characteristics
4.1.3 Turn-On Speed
4.2 APPLICATIONS FOR ON-CHIP ESD PROTECTION
4.2.1 ESD Protection Circuit for the Input/Output Pad
4.2.2 ESD Clamp Circuit between the Power Rails
4.2.3 ESD Robustness
4.2.4 Turn-On Verification
4.3 SUMMARY
FIGURES
CHAPTER 5 SCR DEVICE FABRICATED WITH DUMMY-GATE STRUCTURE
5.1 SCR DEVICE WITH DUMMY-GATE STRUCTURE
5.2 EXPERIMENTAL RESULTS
5.2.1 Device Characteristics
5.2.2 Turn-On Speed
5.2.3 ESD Robustness
5.3 SUMMARY
TABLES
FIGURES
CHAPTER 6 ON-CHIP ESD PROTECTION DESIGN WITH NATIVE-NMOS- TRIGGERED SCR
6.1 NATIVE-NMOS-TRIGGERED SCR (NANSCR) DEVICE
6.1.1 Device Structure
6.1.2 Characteristics of NANSCR
6.2 ON-CHIP ESD PROTECTION DESIGN WITH NANSCR
6.2.1 ESD Protection Circuit for Input/Output Pads
6.2.2 ESD Clamp Circuit between Power Rails
6.2.3 Whole-Chip ESD Protection Scheme
6.3 EXPERIMENTAL RESULTS
6.3.1 Turn-On Verification
6.3.2 EMMI Photographs
6.3.3 TLP Measurement
6.3.4 ESD Robustness
6.4 SUMMARY
TABLES
FIGURES
CHAPTER 7 CONCLUSIONS AND FUTURE WORKS
7.1 MAIN RESULTS OF THIS THESIS
7.2 FUTURE WORKS
REFERENCES
VITA
PUBLICATION LIST

[1] T. J. Green and W. K. Denson, “A review of EOS/ESD field failures in military equipment,” in Proc. EOS/ESD Symp., 1988, pp. 7-14.
[2] ESD Association standard test method for electrostatic discharge sensitivity testing: Human body model-component level, ESD Association, ESD STM 5.1, 2001.
[3] ESD Association standard test method for electrostatic discharge sensitivity testing: Machine model-component level, ESD Association, ESD STM 5.2, 1999.
[4] A. Amerasekera and C. Duvvury, ESD in Silicon Integrated Circuits, 2nd Edition, John Wiley & Sons, Ltd., England, 2002.
[5] C. Duvvury, R. Rountree, and O. Adams, “Internal chip ESD phenomena beyond the protection circuit,” IEEE Trans. Electron Devices, vol. 35, pp. 2133-2139, 1988.
[6] M.-D. Ker and T.-L. Yu, “ESD protection to overcome internal gate oxide damage on digital-analog interface of mixed-mode CMOS IC’s,” in Proc. 7th Europe Symp. Reliability of Electron Device, Failure Physics and Analysis, 1996, pp. 1727-1730.
[7] H. Terletzki, W. Nikutta, and W. Reczek, “Influence of the series resistance of on-chip power supply buses on internal device failure after ESD stress,” IEEE Trans. Electron Devices, vol. 40, pp. 2081-2083, 1993.
[8] C. Johnson, T. Maloney, and S. Qawami, “Two unusual HBM ESD failure mechanisms on a mature CMOS process,” in Proc. EOS/ESD Symp., 1993, pp. 225-231.
[9] M. Chaine, S. Smith, and A. Bui, “Unique ESD failure mechanisms during negative to Vcc HBM tests,” in Proc. EOS/ESD Symp., 1997, pp. 346-355.
[10] M.-D. Ker, C.-Y. Chang, and Y.-S. Chang, “ESD protection design to overcome internal damages on interface circuits of CMOS IC with multiple separated power pins,” in Proc. IEEE Int. SOC Conf., 2002, pp. 234-238.
[11] M.-D. Ker, “Whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits for submicron CMOS VLSI,” IEEE Trans. Electron Devices, vol. 46, pp. 173-183, 1999.
[12] R. N. Rountree, “ESD protection for submicron CMOS circuits: issues and solutions,” in IEDM Tech. Dig., 1988, pp. 580-583.
[13] M.-D. Ker and C.-Y. Wu, “Complementary-SCR ESD protection circuit with interdigitated finger-type layout for input pads of submicron CMOS IC’s,” IEEE Trans. Electron Devices, vol. 42, pp. 1297-1304, 1995.
[14] J. Wu, P. Juliano, and E. Rosenbaum, “Breakdown and latent damage of ultra-thin gate oxides under ESD stress conditions” in Proc. EOS/ESD Symp., 2000, pp. 287-295.
[15] ESD Association standard test method for electrostatic discharge sensitivity testing: Charged device model-component level, ESD Association, ESD STM 5.3.1, 1999.
[16] C. Duvvury and R. Rountree, “A synthesis of ESD input protection scheme,” in Proc. EOS/ESD Symp., 1991, pp. 88-97.
[17] A. Chatterjee and T. Polgreen, “A low-voltage triggering SCR for on-chip ESD protection at output and input pads,” IEEE Electron Device Letters, vol. 12, pp. 21-22, 1991.
[18] M.-D. Ker, C.-Y. Wu, and H.-H. Chang, “Complementary-LVTSCR ESD protection circuit for submicron CMOS VLSI/ULSI,” IEEE Trans. Electron Devices, vol. 43, pp. 588-598, 1996.
[19] M.-D. Ker, H.-H. Chang, and C.-Y. Wu, “A gate-coupled PTLSCR/NTLSCR ESD protection circuit for deep-submicron low-voltage CMOS IC’s,” IEEE J. Solid-State Circuits, vol. 32, pp. 38-51, 1997.
[20] J. T. Watt and A. J. Walker, “A hot-carrier triggered SCR for smart power bus ESD protection,” in IEDM Tech. Dig., 1995, pp. 341-344.
[21] C. Russ, M. P. J. Mergens, J. Armer, P. Jozwiak, G. Kolluri, L. Avery, and K. Verhaege, “GGSCR: GGNMOS triggered silicon controlled rectifiers for ESD protection in deep submicron CMOS processes,” in Proc. EOS/ESD Symp., 2001, pp. 22-31.
[22] M. P. J. Mergens, C. C. Russ, K. G. Verhage, J. Armer, P. C. Jozwiak, and R. Mohn, “High holding current SCRs (HHI-SCR) for ESD protection and latch-up immune IC operation,” in Proc. EOS/ESD Symp., 2002, pp. 10-17.
[23] M.-D. Ker and K.-C. Hsu, “On-chip ESD protection circuit design with novel substrate-triggered SCR device in sub-quarter-micron CMOS process,” in Proc. IEEE International Symposium on Circuits and Systems (ISCAS), 2002, pp. 529-532.
[24] M.-D. Ker and K.-C. Hsu, “Substrate-triggered SCR device for on-chip ESD protection in fully silicided subquarter-micrometer CMOS process,” IEEE Trans. Electron Devices, vol. 50, pp. 397-405, Feb. 2003.
[25] M.-D. Ker and K.-C. Hsu, “Complementary substrate-triggered SCR devices for on-chip ESD protection circuits,” in Proc. IEEE International SOC Conference, 2002, pp. 229-233.
[26] M.-D. Ker and K.-C. Hsu, “Latchup-free ESD protection design with complementary substrate-triggered SCR devices,” IEEE J. Solid-State Circuits, vol. 38, pp. 1380-1392, Aug. 2003.
[27] M.-D. Ker and K.-C. Hsu, “SCR device with double-triggered technique for on-chip ESD protection in sub-quarter-micron silicided CMOS process,” IEEE Trans. Device and Materials Reliability, in press, Sept. 2003.
[28] M.-D. Ker and K.-C. Hsu, “On-chip ESD protection design with native-NMOS-triggered SCR in a 0.13-m CMOS process,” submitted to IEEE J. Solid-State Circuits.
[29] M.-D. Ker and C.-H. Chuang, “Stacked-NMOS triggered silicon-controlled rectifier for ESD protection in high/low-voltage-tolerant I/O interface,” IEEE Electron Device Letters, vol. 23, pp. 363-365, 2002.
[30] M.-D. Ker and C.-H. Chuang, “ESD protection design for mixed-voltage CMOS I/O buffers,” IEEE J. Solid-State Circuits, vol. 37, pp. 1046-1055, 2002.
[31] M.-D. Ker and K.-C. Hsu, “Overview on the on-chip electrostatic discharge protection design with SCR-based devices in CMOS integrated circuits,” submitted to Proceedings of the IEEE.
[32] G. Weiss and D. Young, “Transient-induced latchup testing of CMOS integrated circuits,” in Proc. EOS/ESD Symp., 1995, pp. 194-198.
[33] A. Amerasekera, S. Ramaswamy, M.-C. Chang, and C. Duvvury, “Modeling MOS snapback and parasitic bipolar action for circuit-level ESD and high current simulations,” in Proc. IEEE Int. Reliability Physics Symp., 1996, pp. 318-326.
[34] H. Wong, “A physically-based MOS transistor avalanche breakdown model,” IEEE Trans. Electron Devices, vol. 42, pp. 2197-2002, 1995.
[35] M.-D. Ker and C.-Y. Wu, “Modeling the positive-feedback regenerative process of CMOS latchup by a positive transient pole method-part I: theoretical derivation,” IEEE Trans. Electron Devices, vol. 42, pp. 1141-1148, 1995.
[36] M.-D. Ker and C.-Y. Wu, “Modeling the positive-feedback regenerative process of CMOS latchup by a positive transient pole method-part II: quantitative evaluation,” IEEE Trans. Electron Devices, vol. 42, pp. 1149-1155, 1995.
[37] C. Duvvury, T. Tayler, J. Lindgren, J. Morris, and S. Kumar, “Input protection design for overall chip reliability,” in Proc. EOS/ESD Symp., 1989, pp. 190-197.
[38] M.-D. Ker, C.-Y. Wu, T. Cheng, and H.-H. Chang, “Capacitor-coupled ESD protection circuit for deep-submicron low-voltage CMOS ASIC,” IEEE Trans. VLSI Systems, vol. 4, pp. 307-321, 1996.
[39] S. Ramaswamy, A. Amerasekera, and M.-C. Chang, “A unified substrate current model for weak and strong impact ionization in sub-0.25m NMOS devices,” in IEDM Tech. Dig., 1997, pp. 885-888.
[40] K.-C. Hsu and M.-D. Ker, “Improvement on turn-on speed of substrate-triggered SCR device by using dummy-gate structure for on-chip ESD protection,” in Proc. International Conference on Solid State Devices and Materials, Sept. 2003, in press.
[41] M.-D. Ker and G.-L. Lin, “Low-voltage-triggered electrostatic discharge protection device and relevant circuitry,” US patent #6,465,848, Oct. 2002.
[42] M.-D. Ker and K.-C. Hsu, “SCR device fabricated with dummy-gate structure to improve turn-on speed for effective ESD protection,” submitted to IEEE Trans. Semiconductor Manufacturing.
[43] A. Z. H. Wang and C.-H. Tsay, “An on-chip ESD protection circuit with low trigger voltage in BiCMOS technology,” IEEE J. Solid-State Circuits, vol. 36, pp. 40-45, 2001.
[44] M.-D. Ker and C.-Y. Wu, “CMOS on-chip electrostatic discharge protection circuit using four-SCR structures with low ESD-trigger voltage,” Solid-State Electronics, vol. 37, pp. 17-26, 1994.
[45] C. Duvvury, J. Rodriguez, C. Jones, and M. Smayling, “Device integration for ESD robustness of high voltage power MOSFETs,” in IEDM Tech. Dig., 1994, pp. 407-410.
[46] K. Kunz, C. Duvvury, and H. Shichijo, “5-V tolerant fail-safe ESD solutions for 0.18m logic CMOS process,” in Proc. EOS/ESD Symp., 2001, pp. 12-21.
[47] J.-H. Lee, J.-R. Shih, C.-S. Tang, K.-C. Liu, Y.-H. Wu, R.-Y. Shiue, T.-C. Ong, Y.-K. Peng, and J.-T. Yue, “Novel ESD protection structure with embedded SCR LDMOS for smart power technology,” in Proc. IEEE Int. Reliability Physics Symp., 2002, pp. 156-161.
[48] C. Delage, N. Nolhier, M. Bafleur, J.-M. Dorkel, J. Hamid, P. Gicelin, and J. Lin-Kwang, “The mirrored lateral SCR (MILSCR) as an ESD protection structure: design and optimization using 2-D device simulation,” IEEE J. Solid-State Circuits, vol. 34, pp. 1283-1289, 1999.
[49] M.-D. Ker, “Lateral SCR devices with low-voltage high-current triggering characteristics for output ESD protection in submicron CMOS technology,” IEEE Trans. Electron Devices, vol. 45, pp. 849-860, 1998.
[50] G. Notermans, F. Kuper, and J.-M. Luchis, “Using an SCR as ESD protection without latchup danger,” Microelectronics Reliability, vol. 37, pp. 1457-1460, 1997.
[51] M.-D. Ker and H.-H. Chang, “How to safely apply the LVTSCR for CMOS whole-chip ESD protection without being accidentally triggered on,” in Proc. EOS/ESD Symp., 1998, pp. 72-85.
[52] Z.-P. Chen and M.-D. Ker, “Dynamic holding voltage SCR (DHVSCR) device for ESD protection with high latch-up immunity,” in Proc. International Conference on Solid State Devices and Materials, Sept. 2003, in press.
[53] S. Aur, A. Chatterjee, and T. Polgreen, “Hot-electron reliability and ESD latent damage,” IEEE Trans. Electron Devices, vol. 35, pp. 2189-2193, 1988.
[54] K. R. Mistry, D. Krakauer, and B. S. Doyle, “Impact of snapback-induced hole injection on gate oxide reliability of N-MOSFET’s,” IEEE Electron Device Letters, vol. 11, pp. 460-462, 1990.
[55] S. Krishnan and A. Amerasekera, “Antenna protection strategy for ultra-thin gate MOSFETs,” in Proc. IEEE Int. Symp. on Reliability Physics, 1998, pp. 302-306.
[56] T. J. Maloney and N. Khurana, “Transmission line pulsing techniques for circuit modeling of ESD phenomena,” in Proc. EOS/ESD Symp., 1985, pp. 49-54.
[57] J. Barth, J. Richner, K. Verhaege, and L. G. Henry, “TLP calibration, correlation, standards, and new techniques,” in Proc. EOS/ESD Symp., 2000, pp. 85-96.
[58] R. R. Troutman, Latchup in CMOS technology. Boston, MA: Kluwer, 1986.
[59] M. P. J. Mergens, K. G. Verhage, C. C. Russ, J. Armer, P. C. Jozwiak, G. Kolluri, and R. Avery, “Multi-finger turn-on circuits and design techniques for enhanced ESD performance and width-scaling,” in Proc. EOS/ESD Symp., 2001, pp. 1-11.
[60] G.-L. Lin and M.-D. Ker, “Fabrication of ESD protection device using a gate as a silicide blocking mask for a drain region,” US patent #6,046,087, Apr. 2000.
[61] C.-S. Kim, H.-B. Park, Y.-G. Kim, D.-G. Kang, M-G. Lee, S.-W. Lee, C.-H. Jeon, H.-G. Kim, Y.-J. Yoo, H.-S. Yoon, “A novel NMOS transistor for high performance ESD protection device in 0.18m CMOS technology utilizing salicide process,” in Proc. EOS/ESD Symp., 2000, pp. 407-412.
[62] V. Gupta, A. Amerasekera, S. Ramaswamy, and A. Taso, “ESD-related process effects in mixed-voltage sub-0.5m technologies,” in Proc. EOS/ESD Symp., 1998, pp. 161-169.
[63] M.-D. Ker, C.-Y. Chang, and H.-C. Jiang, “Design of negative charge pump circuit with polysilicon diodes in a 0.25-m CMOS process,” in Proc. IEEE AP-ASIC Conference, 2002, pp. 145-148.

QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top
系統版面圖檔 系統版面圖檔