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研究生:卓煜盛
研究生(外文):Caleb Yu-Sheng Cho
論文名稱:創新式高可靠度的快閃記憶體---特性、可靠性評估及應用
論文名稱(外文):A Novel Highly Reliable Flash Memory --- Characteristics, Reliability Evaluations, and Applications
指導教授:陳明哲陳明哲引用關係
指導教授(外文):Ming-Jer Chen
學位類別:博士
校院名稱:國立交通大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2004
畢業學年度:92
語文別:英文
論文頁數:98
中文關鍵詞:快閃記憶體耦合參數分離閘可靠性多準位抹除寫入
外文關鍵詞:Flash memorycoupling ratiosplit-gatereliabilitymultileveleraseprogramNAND
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在本論文中,一種高可靠度的sidewall-gate快閃式記憶體被引進,並且用最先進的三層複晶矽0.15微米製程而得。這個新奇的結構不僅能用在程式碼儲存(code storage)應用的NOR陣列結構,並且還可廣泛應用在大量儲存(mass storage)方面的NAND陣列結構。由於美國專利申請法規中說明,在專利接受之前,任何的著作中皆不得提及該申請的內容,所以本論文中便不提及NAND結構的應用。在本文的起頭,我們描述了市場上主流的三種快閃記憶體結構,即NOR型結構的堆疊式(stacked gate)、分離閘式(spilt-gate)及NAND型結構的堆疊式快閃記憶體,並簡述其優缺點。由於本創新結構(sidewall-gate)有諸多和分離閘快閃記憶體相似的優點,再加上它擁有部份市面上商用分離閘式快閃記憶體所欠缺的尺寸高微縮(dimensional scaling)的優點,本sidewall-gate快閃式記憶體問世並廣泛使用的潛力可期。
眾所周知,閘極電容耦合參數(gate capacitive coupling coefficient)對於電子寫入(program)與抹除(erase)扮演了一個非常重要的角色。第一次,我們提出了一個新奇,且快又準的萃取方法用來萃取這個值。不需繁複的手續、儀器及計算,這個新技巧提供對於自動化監控程序的可能性。完整了解該參數會幫助快閃記憶體的設計及技術開發工程師們能有效地設定操作電壓及脈衝時間的最佳化。這個技巧不僅提供了理論上的價值,更重要的是,它為工業方面的應用找到一個出口。
對於這個創新的sidewall-gate快閃記憶體而言,源極側通道熱電子注入(source-side channel hot electron injection)是用在寫入的操作,用以將電子注入浮動閘(floating gate);另一方面,電子則由浮動閘往相鄰的選擇閘(select gate)方向以富勒-諾得漢穿隧(Fowler-Nordheim tunneling)的方式,完成電子由浮動閘抹除的動作;若以材料構成名稱而言,則簡稱為『複晶閘-對-複晶閘抹除』(poly-to-poly erase)。對於新式sidewall-gate快閃記憶體而言,我們刻意製造的『弧形浮動閘邊牆』(rounded floating-gate sidewall)有助於減輕來自於多次重複寫入/抹除動作對於閘極間氧化層(interpoly oxide)的傷害(雖然電子在這個區域被捕捉是不可避免的),這主要歸因於:電力線在這個弧形浮動閘邊牆不再是密集的高電場,這緩和了過高的邊角(corner)電場對閘極間氧化層的劣化;雖然,穿隧用的電場被降低了,可是依照不同抹除記憶胞(memory cell)數目大小而言,所需之10到20毫秒的過度抹除(overerase)時間仍是可接受的。多虧了選擇閘元件內存在此sidewall-gate記憶體中,就算記憶胞被過度抹除,在判讀上仍不會有不想要的顯著漏電流干擾。這種與生俱來的『過度抹度免疫力』(overerase immunity)使得傳統用來防止此問題的步驟省了,並且省下的面積可以容納更多的記憶胞陣列。
至於大家所關心的可靠性議題,諸如耐用性測試(endurance),高溫下的資訊持久性(retention bake)及內存資訊受干擾的效應(disturb effects)不僅在單顆記憶胞上有所研究,對於百萬顆記憶胞量級的記憶陣列(Mega-bit array)也是測量樣本。由可靠性議題的結果及分析,適合的操作電壓及脈衝時間也在可靠性因素的前提下被檢驗。關於最近備受關注的多準位觀念(multilevel concept),對於新式sidewall-gate快閃記憶體用在此方面的研究也有簡短探討,之後更詳細的研究及應用則是未來的方向。
簡言之,sidewall-gate快閃記憶體有著以下幾個令人驚豔的優點:(1)它的單位記憶胞面積大小只有12.7 F平方(F是feature size),和堆疊式快閃記憶體的單位記憶胞面積10 F平方相近;(2)其天生的過度抹除免疫功能免除了多餘且複雜的過度抹除防止機制,進而加大了記憶胞陣列的面積;(3)對於像『汲極導通』(drain turn-on)及『貫穿』(punchthrough)等短通道引起的不良效應(short-channel effects),多虧了選擇閘的存在而少受其影響;以及(4)低功率消粍,及高電子寫入效率等,都是曾經被報導的。
In this dissertation, a novel highly reliable Flash memory is introduced in state-of-the-art 0.15-micrometer technologies, and 3-poly process is used to fabricate the sidewall-gate novel Flash memories. At first time, a 3-poly Flash memories are utilized in both NOR and NAND architectures for code storage and mass storage applications successfully. Due to U.S. patent rules, the NAND application by the novel cell is not mentioned in this work. Three main structures (stacked gate and split-gate in NOR, and stacked gate in NAND) are described in Chapter 1 for a comparison survey, and the novel sidewall-gate Flash is highly potential due to the advantages of split-gate Flash and scaling benefit which are not owned by some commercial split-gate devices.
Gate capacitive coupling coefficient plays a crucial factor for programming and erasure operations. At first time, a novel, fast and precise extraction technique gate coupling coefficient is proposed. No complex procedures, instruments or calculations are needed; and the novel technique is beneficial for automatic routine in process monitor. Well understanding of gate coupling coefficient makes Flash designers and technology developers can set up optimum operating voltages. This novel technique provides not only the underlying physics, but also actual industrial application.
High-efficiency source-side channel hot electron injection is applied for electron injection onto floating gate (i.e., programming), and poly-to-poly erase by Fowler-Nordheim tunneling from floating-gate sidewall towards neighboring select gate is exploited. Due to the deliberately shaped round sidewall of floating gate (FG), the damage to interpoly oxide from repeated program/erase (P/E) cycles can be alleviated. Although the electrons trapping in this area is inevitable, some merits are kept due to this rounded shape. First, the field lines around FG corner are less densely concentrated and the reduced electric field alleviates the degradation to interpoly oxide. Second, the poly-to-poly erase scheme can erase the device to an over-erased state in 10 ~ 20 ms (depending on the erase size) without influence of remarkable leakage current during read-out. Thanks to the select-gate part of the novel Flash, this inherent overerase immunity makes traditional overerase procedures in vain and enlarges the cell array area.
The concerned reliability issues such as endurance testing, retention bake and disturb effects are fully characterized not only on single cell level, but also on Mega-bit array for detailed distribution. From the reliability discussion, suitable operating voltages and pulse durations are verified for reliable reasons. As far as the multilevel concept is concerned recently, brief discussion on realization by the novel Flash is unveiled, and the implementation will be left as future works.
In summary, we listed main advantages of the sidewall-gate Flash as follows: (i) a competitive unit cell size of 12.7 feature size square, which is comparable to 10 feature size square of stacked gate cell; (ii) the inherent overerase immunity of the novel Flash, which makes complicated overerase procedures spared and thus enlarges cell array area; (iii) less susceptibility to short-channel effects (drain turn-on and punchthrough); and (iv) low power consumption and high program efficiency dedicated to sidewall-gate Flash memories.
Chinese Abstract i
English Abstract iii
Acknowledgements v
Table of Contents vii
Table Captions xi
Figure Captions xiii
List of Symbols xix
Chapter 1: Introduction 1
1.1 Flash memory market and applications 1
1.2 Brief introduction for floating-gate device history 1
1.3 Industrial Flash architectures 2
1.3.1 NOR architecture 3
1.3.1.1 Stacked gate structure 3
1.3.1.2 Split-gate structure 6
1.3.1.3 Sidewall-gate structure 7
1.3.2 NAND architecture 8
1.4 Purpose of this work 9
References 12
Chapter 2: Gate capacitive coupling extraction 15
2.1 Gate capacitive coupling coefficient alphaG 15
2.2 Existing and new subthreshold slope methods 16
2.2.1 Subthreshold swing ratio method (SS) 16
2.2.2 Subthreshold swing ratio method involving bulk coupling (SSB) 16
2.2.3 Process-variation-immunity method (PVI) 17
2.2.4 New method 17
2.3 Results and discussion 19
2.3.1 Stacked gate structure: results and discussion 19
2.3.2 Source-side injection structure: results and discussion 23
2.4 Summary 25
References 26
Chapter 3: Characteristics of the novel Flash memory 29
3.1 Novel sidewall-gate Flash memory 29
3.2 Key process of novel sidewall-gate Flash cell 30
3.3 Physics of the novel Flash 30
3.3.1 Physics of program operation 31
3.3.2 Physics of erase operation 32
3.4 dc measurements 33
3.4.1 Gate capacitive coupling coefficient alpha G 34
3.4.2 Intrinsic characteristic of overerase immunity 34
3.4.3 Biasing voltages under program operation 36
3.5 Cells operations in a NOR array 36
3.6 Characteristics of program and erase 38
3.6.1 Program characteristics 39
3.6.2 Erase characteristics 39
3.7 Summary 42
References 43
Chapter 4: Reliability issues of the novel Flash memory 45
4.1 Endurance characteristics 45
4.1.1 Short survey 45
4.1.2 Physics of charge trapping behavior in novel Flash 46
4.1.3 Vth window behavior of the novel Flash 48
4.1.4 Vs dependence 49
4.1.5 Comparison to source-side erase 51
4.2 Retention bake in high temperature 51
4.3 Disturb effects 53
4.3.1 Program inhibition 53
4.3.2 Program Disturbs 53
4.3.3 Read-out disturb 56
4.4 Summary 57
References 58
Chapter 5: Multilevel approach 59
5.1 Introduction to multilevel concept 59
5.2 FBECHEI for ML realization in SGC 60
5.2.1 Experimental 61
5.2.2 Results and Linear Relation 62
5.2.3 Extra Measurements 64
5.2.4 Brief summary 67
5.3 Multilevel approach in novel sidewall-gate Flash 68
5.4 Summary 69
References 70
Chapter 6: Conclusions 73
Vita 75
Publication List 76
◆ Chapter 1
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◆ Chapter 2
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[3] C. Y.-S. Cho, M.-J. Chen, and C.-F. Chen, “Fast and precise subthreshold slope method for extracting gate capacitive coupling coefficient in Flash memory cells,” in Proc. IEEE 2003 Int. Conference on Microelectronic Test Structures, 2003, pp. 186190.
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[7] W. L. Choi and D. M. Kim, “A new method for measuring coupling coefficients and 3-D capacitance characterization of floating-gate devices,” IEEE Trans. Electron Devices, vol. 41, pp. 23372342, Dec. 1994.
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◆ Chapter 3
[1] C. Hu, S. C. Tam, F.-C. Hsu, P.-K. Ko, T.-Y. Chan, and K. W. Terrill, “Hot-electron-induced MOSFET degradationModel, monitor, and improvement,” IEEE Trans. Elect. Dev., vol. ED-32, p. 375, 1985.
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◆ Chapter 4
[1] S. Yamada, Y. Hiura, T. Yamane, K. Amemiya, Y. Ohshima, and K. Yoshikawa, “Degradation mechanism of Flash EEPROM programming after program/erase cycles,” IEDM Tech. Digest, 1993, pp. 2326.
[2] I. C. Chen, S. Holland, and C. Hu, “Electron-trap generation by recombination of electrons and holes in SiO2,” J. Appl. Phys., vol. 61, pp. 4544  4548, May 1987.
[3] M. Kimura and H. Koyama, "Stress-induced low-level leakage mechanism in ultrathin silicon dioxide films caused by neutral oxide trap generation," in Proc. Int. Reliability Phys. Symp., 1994, pp. 167  172.
[4] J. De Blauwe, J. Van Houdt, D. Wellekens, G. Groeseneken, and H. E. Maes, “SILC-related effects in flash E2PROM’s―part II: prediction of steady-state SILC-related disturb characteristics,” IEEE Trans. Electron Devices, vol. 45, pp. 17511760, Aug. 1998.
[5] J. Van Houdt, G. Groeseneken, and H. E. Maes,” An analytical model for the optimization of high injection MOS Flash E2PROM devices,” Microelectronic Engineering, vol. 19, pp. 257—260, 1992.
[6] D. Wellekens, J. Van Houdt, L. Faraone, G. Groeseneken, and H. E. Maes, “Write/erase degradation in source side injection Flash EEPROM’s: Characterization techniques and wearout mechanisms,” IEEE Trans. Elect. Dev., vol. 42, pp. 1992—1998, Nov. 1995.
[7] J. Van Houdt, L. Haspeslagh, D. Wellekens, L. Deferm, G. Groeseneken, and H. E. Maes, “HIMOS─A high efficiency Flash E2PROM cell for embedded memory applications,” IEEE Trans. Elect. Dev., vol. 40, pp. 2255—2263, Dec. 1993.
[8] J. Van Houdt, D. Wellekens, L. Faraone, L. Haspeslagh, L. Deferm, “A 5 V-compatible Flash EEPROM cell with microsecond programming time for embedded memory applications,” IEEE Trans. Comp., Packag., Manufact. Technol. A, vol. 17, pp. 380389, Sep. 1994.
[9] K. Naruke, S. Yamada, E. Obi, S. Taguchi, and M. Wada, “A new Flash erase EEPROM cell with a sidewall select-gate on its source side,” IEDM Tech. Digest, 1989, pp. 603606.
[10] G. Groeseneken and H. E. Maes, “A quantitative model for the conduction in oxides thermally grown from polycrystalline silicon,” IEEE Trans. Elect. Dev., vol. ED-33, pp. 10281042, July 1986.
◆ Chapter 5
[1] M. Grossi, M. Lanzoni, and B. Riccò, “Program scheme for multilevel Flash memories,” Proc. IEEE, vol. 91, pp. 594601, Apr. 2003.
[2] B. Riccò, G. Torelli, M. Lanzoni, A. Manstretta, H. E. Maes, D. Montanari, and A. Modelli, “Nonvolatile multilevel memories for digital applications,” Proc. IEEE, vol. 86, pp. 23992421, Dec. 1998.
[3] C. Calligaro, A. Manstretta, A. Modelli, and G. Torelli, “Technological and design constraints for multilevel Flash memories,” in Proc. 3rd IEEE Int. Conf. Electronics, Circuits and Systems, Oct. 1996, pp. 10031008.
[4] A. Modelli, A. Manstretta, and G. Torelli, “Basic feasibility constraints for multilevel CHE-programmed Flash memories,” IEEE Trans. Electron Devices, vol. 48, pp. 20322042, Sep. 2001.
[5] M.-H. Chi and A. Bergemont, “Multi-level Flash/EPROM memories: new self-convergent programming methods for low-voltage applications,” IEDM Tech. Digest, 1995, pp. 271274.
[6] C. Y.-S. Cho, M.-J. Chen, and C.-F. Chen, “Fast and precise subthreshold slope method for extracting gate capacitive coupling coefficient in flash memory cells,” in Proc. IEEE 2003 Int. Conference on Microelectronic Test Structures, 2003, pp. 186190.
[7] S. Kianian, A. Levi, D. Lee, and Y.-W. Hu, “A novel 3 volts-only, small sector erase, high density Flash E2PROM,” VLSI Tech. Dig., 1994, pp. 7172.
[8] S. Yamada, Y. Hiura, T. Yamane, K. Amemiya, Y. Ohshima, and K. Yoshikawa, “Degradation mechanism of Flash EEPROM programming after program/erase cycles,” IEDM Tech. Digest, 1993, pp. 2326.
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