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研究生:林子貴
論文名稱:蒙地卡羅在靜態記憶體上的應用:良率改善與最佳化
論文名稱(外文):An application of Monte-Carlo on SRAM: improvement & optimization
指導教授:吳錦川
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電資學院學程碩士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2003
畢業學年度:92
語文別:英文
論文頁數:57
中文關鍵詞:蒙地卡羅記憶體最佳化
外文關鍵詞:Monte-CarloSRAMoptimization
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在設計靜態隨機存取記憶體之記憶體單元時,要求面積小速度快又要保持高品質高良率一直是各晶圓代工廠所追求之目標。
早期(0.18微米之前),靜態隨機存取記憶體之記憶體單元有著相對較厚的閘級氧化層,可抑制漏電流,而且此時之操作電壓也維持在1.5伏以上,這些都使得靜態隨機存取記憶體在各種操作條件下都有足夠的電性雜訊容忍度,此時記憶體單位設計目標多著重在面積大小與製程上的發展上。
隨著製程的演進,當接近次微米(0.13微米甚至90奈米以下)時,靜態隨機存取記憶體之記憶體單元有著相對較薄的閘級氧化層,使之逐漸產生較大的漏電流,而伴隨較低的操作電壓,使得靜態隨機存取記憶體更難在各種操作條件下仍然保持足夠的電性雜訊容忍度。假若記憶體單位設計目標依然放在面積的大小與製程的發展上而忽略了電性低品質的影響,此時很容易產生低良率的情形。
本論文以「A公司」的次微米靜態隨機存取記憶體為研究對象,並將提出一套“靜態隨機存取記憶體在蒙地卡羅的分析方法 ”,試圖找出其影響品質及良率的重要電性特性以及其分佈。並藉由這套“蒙地卡羅在靜態隨機存取記憶體的分析方法”得到最佳化的設計方法。最後藉由這套最佳化設計方法,我們將提供一個晶圓代工廠對靜態隨機存取記憶體工廠改善的目標與方向。而這個 “蒙地卡羅在靜態隨機存取記憶體的分析方法”及“最佳化方法”,我們可以得到一個不僅滿足面積速度更可以得到高品質高良率率的最佳化設計。

While design a SRAM (Static random access memory) bit cell, High speed and small area with high yield always is the target of Foundry.
At early process, (before as 0.18um), the thick gate oxide will prevent leakage current and the operation voltage of SRAM always above 1.5V. It will lead sufficient electrical margin at every corner condition. For that moment all SARM bit cell design target always focus on area and process development.
For modern process, (afterward 0.13um), the thin gate oxide always suffer leakage issue and low operation voltage of SRAM will be difficult to keep electrical margin at some corner condition. It will occur low yield and worse performance if we still focus on SRAM cell size and process tuning but ignore the SRAM electrical margin effect.
In this thesis, we discuss and study “Company-A” sub-micro SRAM. We will propose a “Monte-Carlo analysis methodology for SRAM” to find out the distribution of performance and get the optimum design. Finally we will point out a reasonable target for Foundry future improvement reference. By way of optimization research and method, we can find a SRAM bit cell design, which satisfy the area, speed and high yield.

Contents
Abstract …………………………………………………………………………….…. vii
Acknowledgement ………………………………………………………..………. viii
Contents …………………………………………………………………….….………. ix
List of tables ………………………………………………………..………………… xi
List of Figures ……………………………………………………….………………. xii
List of Acronyms …………………………………………………………………….xiv
Chapter-1 Introduction
1.1 Review the contemporary SRAM bit cell design methodology ………………….…… .. 1
1.2 The motive and intention of this thesis ………………………………………….………. 2
1.3 The thesis organization ……………………………………………………...………...… 3
1.4 Basic assumption ………………………………………………………………………… 4
Chapter-2 Basic SRAM diagram and functionality
2.1 SRAM functional operation diagram …………………………………………..………… 5
2.2 SRAM memory architecture and schematic …………………………………..……...….. 6
2.3 The SRAM bit cell ……………………………………………………………………….. 7
2.4 The SRAM bit cell characteristic ………………………………………………………… 9
Chapter-3 Monte-Carlo simulation methodology on SRAM analysis
3.1 SRAM Monte-Carlo simulations vs. SPICE corners …………………………………… 16
3.2 Establish SRAM Monte-Carlo methodology …………………………………………… 18
3.3 Check SRAM performance from Monte-Carlo simulation ………………….………….. 21
3.4 Brief summary for current SRAM design ……………………………...……………….. 22
Chapter-4 Monte-Carlo analysis methodology for SRAM optimization
4.1 Primary optimization idea ………………………………………………………………. 31
4.2 Optimum by modifyingβ-ratio method …………………………………………….….. 32
4.3 Optimum by adjusting Vth-implant method ………………………………………...….. 33
4.4 Optimization flow for SRAM new design ……………………………………………… 34
Chapter-5 Monte-Carlo analysis methodology for SRAM improvement
5.1 Possibility yield by different mismatch simulation ………………………………..……. 44
5.2 Simulation result by process control improvement and Vth optimum ………...……….. 45
Chapter-6 Summary & Future work
6.1 Brief result and summary for this thesis …………………………………….………….. 49
6.2 Future work ……………………………………………………………………….…….. 49
References ……………………………………………………………….……………….. 55
List of Tables
Table-3.1 SRAM SPICE model skew parameter table ………………………………………23
Table-3.2 Monte-Carlo simulation result with independent skew parameter ………………..23
Table-3.3 The cover range of Monte-Carlo simulation result with independent skew parameter
…………………………………………………………………………………………..…… 23
Table-3.4 I-cell &β-ratio Monte-Carlo simulation result with independent skew parameter
…………………………………………………………………………………………..…… 24
Table-3.5 Monte-Carlo simulation result with NMOS dependent skew parameter …….…... 24
Table-3.6 The cover range of Monte-Carlo simulation result with NMOS dependent skew parameter …………….………………………………………………………………....…… 24
Table-3.7 I-cell &β-ratio Monte-Carlo simulation result with NMOS dependent skew parameter …………….………………………………………………………………....…… 25
Table-3.8 Sensitivity table based on Monte-Carlo simulation ………………………....…… 25
Table-3.9 Variance parameter for Monte-Carlo based on WAT …………….…...…....…… 25
Table-3.10 Monte-Carlo simulation result with WAT skew parameter ……………….…… 26
Table-3.11 The cover range of Monte-Carlo simulation result with WAT skew parameter
…………………………………………………………………………………………..…… 26
Table-6.1 SRAM bit-cell comparison …...……………………………………………..…… 54
Table-6.2 The advantage and disadvantage between different styles SRAM ……….……… 54
List of Figures
Fig-2.1 Block diagram for SRAM macro …………………………………….………..…… 11
Fig-2.2 Timing waveform of write cycle …………………………………….………...…… 11
Fig-2.3 Timing waveform of read cycle …………………………………….………..…..… 12
Fig-2.4 SRAM schematic diagram ………………………………………...….………..…… 12
Fig-2.5 typical of 6T SRAM bit-cell …………………………………….……………..…… 13
Fig-2.6 Write operation of 6T SRAM bit-cell ………………………………..………..…… 13
Fig-2.7 Read operation of 6T SRAM bit-cell ……………………………..….………..…… 14
Fig-2.8 The bit-line leakage schematic …………………………………….…………..…… 14
Fig-2.9(a) Waveform of bit-line of ideal case without bit-line leakage …………………….. 15
Fig-2.9(b) Waveform of bit-line without bit-line leakage ………………………………….. 15
Fig-2.10 Circuit schematic of SRAM SNM …………………………...……………………. 15
Fig-2.11 SRAM SNM butterfly curve ………………………………………..…………….. 16
Fig-3.1 SRAM PG Vth & Idsat WAT data ………………………………………...……….. 27
Fig-3.2 SRAM PD Vth & Idsat WAT data ………………………………………...……….. 27
Fig-3.3 SRAM I-cell WAT data ………………………………….…………..…………….. 27
Fig-3.4 SRAMβ-ratio WAT data ……………………………………………....………….. 27
Fig-3.5 Monte-Carlo simulation flow …………...……………………………....………….. 28
Fig-3.6 I-cell distribution by Monte-Carlo simulation …………………….…....………….. 28
Fig-3.7 On/off ratio distribution by Monte-Carlo simulation at high temperature …………. 29
Fig-3.8 SNM distribution by Monte-Carlo simulation at room temperature …….…………. 29
Fig-3.9 SNM distribution by Monte-Carlo simulation at high temperature …….…….……. 30
Fig-4.1 Primary optimization methodology ………………………………………………... 35
Fig-4.2 I-cell (mean value) vs.β-ratio (mean value) relation ……………………………… 36
Fig-4.3 On/off-ratio (mean value) vs.β-ratio (mean value) relation ………………………. 36
Fig-4.4 SNM (mean value) vs.β-ratio (mean value) relation ……………………………… 37
Fig-4.5 Cell size vs.β-ratio (mean value) relation …………………………………………. 37
Fig-4.6 I-cell distribution by differentβ-ratio ……………………………………………… 38
Fig-4.7 On/off-ratio distribution by differentβ-ratio ………………………………………. 38
Fig-4.8 SNM distribution by differentβ-ratio ………………...…………………………… 39
Fig-4.9 Possibility yield by differentβ-ratio …………………..…………………………… 39
Fig-4.10 I-cell (mean value) vs. dVth (mean value) relation ……………………………….. 40
Fig-4.11 On/off-ratio (mean value) vs. dVth (mean value) relation …………………….….. 40
Fig-4.12 SNM (mean value) vs. dVth (mean value) relation ……………………………….. 41
Fig-4.13 I-cell distribution by different Vth ……………………………...…..…………….. 41
Fig-4.14 On/off-ratio distribution by different Vth ……………………………………..….. 42
Fig-4.15 SNM distribution by different Vth ………………………………………….…….. 42
Fig-4.16 Possibility yield by different Vth …………………………………………...…….. 43
Fig-4.17 Proposal SRAM new design flow ……………………………………….….…….. 43
Fig-5.1 Possibility yield with different Vth and Mismatch ………………….……….…….. 46
Fig-5.2 Possibility yield by process tighten only ……………………………………..…….. 46
Fig-5.3 Improvement by tighten mismatch control with optimum Vth …………………….. 47
Fig-5.4 I-cell distribution by improvement target …………………………………….…….. 47
Fig-5.5 On/off-ratio distribution by improvement target …………………………..……….. 48
Fig-5.6 SNM distribution by improvement target ………………………………………….. 48
Fig-6.1 Common VSS style SRAM layout …………………….………………………….. 51
Fig-6.2 Schematic of common VSS style SRAM …………………………………………. 51
Fig-6.3 Separate VSS style SRAM layout …………………………………………………. 52
Fig-6.4 Schematic of separate VSS style SRAM …………………………………..………. 52
Fig-6.5 Split Word-Line style SRAM layout ………………………………………….……. 53
Fig-6.6 Split Word-Line style SRAM ………………………………………………………. 53

Reference
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[3] E. Seevinck, et., al., “Static-noise margin analysis of MOS SRAM cells, ” JSSC, Oct. 1987.
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[12] Michael Orshansky; and James C. Chen; and Chenming Hu; “A Statistical Performance Simulation Methodology for VLSI Circuits,” in Design Automation Conference, pp. 402 —407, June 1998.
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[16] Yo-Sheng Lin; Chung-Cheng Wu; Chih-Sheng Chang; Rong-Ping Yang; Wei-Ming Chen; Jhon-Jhy Liaw; Diaz, C.H.; “Leakage scaling in deep submicron CMOS for SoC” Electron Devices, IEEE Transactions on, Volume 49, pp. 1034 —1041, June 2002.
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