|
[1] T. Ghani, S. Ahtned, P. Aminzadeh, J. Bielefeld, P. Charvat, C. Chu, M. Harper, P. Jacob, C. Jan, J. Kavalieros, C. Kenyon, R. Nagisetty, P. Packan, J. Sebastian, M. Taylor, J. Tsai, S. Tyagi, S. Yang, and M. Bohr, “100 nm gate length high performance/low power CMOS transistor structure,” in IEDM Tech. Dig., Dec. 1999, pp. 415-418. [2] R. Chau, J. Kavalieros, B. Roberds, R. Schenker, D. Lionberger, D. Barlage, B. Doyle, R. Arghavani, A. Murthy, and G. Dewey, “30 nm physical gate length CMOS transistors with 1.0 ps n-MOS and 1.7 ps p-MOS gate delays,” in IEDM Tech. Dig., Dec. 2000, pp. 45-49. [3] T. Ghani, K. Mistry, P. Packan, S. Thompson, M. Stettler, S. Tyagi, M. Bohr, “Scaling challenges and device design requirements for high performance sub-50 nm gate length planar CMOS transistor,” Symp. on VLSI Tech., pp. 174-175, Jane 2000. [4] “International Technology Roadmap for Semiconductors,” Semiconductor Industry Assoc., San Jose, CA, 2003 [5] J. H. Stathis and D. J. DiMaria, “Reliability projection ultra-thin at low voltage,” in IEDM Tech. Dig., 1998, pp. 167-170. [6] M. A. Alam, J. Bude, and A. Ghetti, “Field acceleration for oxide breakdown – can an accurate anode hole injection model resolve the E vs. 1/E controversy?,” in Proc. IRPS, April, 2000, pp. 21-26. [7] J. H. Stathis, “Physical and predictable models of ultrathin oxide reliability in CMOS devices and circuits,” in Proc. IRPS, May 2001, pp. 132-149. [8] M. Takayanagi, S. Takagi, and Y. Toyoshima, “Experimental study of gate voltage scaling for TDDB under direct tunneling regime,” in Proc. IRPS, May 2001, pp. 380-385. [9] L. F. Register, E. Rosenbaum, and K. Yang, “Analytic model for direct tunneling current in polycrystalline silicon-gate metal-oxide-semiconductor devices,” Appl. Phys. Lett., vol. 74, pp. 457-459, Jan. 1999. [10] N. Yang, W. K. Henson, J. R. Hauser, and J. J. Wortman, “Modeling study of ultra thin gate oxides using direct tunneling current and capacitance-voltage measurements in MOS devices,” IEEE Trans. Electron Devices, vol. 46, pp. 1464–1471, July 1999. [11] S.-I. Takagi, M. Takayanagi-Takagi, and A. Toriumi, “Accurate characterization of electron and hole inversion-layer capacitance and its impact on low voltage operation of scaled MOSFETs,” in IEDM Tech. Dig., 1998, pp. 619-622. [12] N. G. Gunther, A. A. Mutlu, and M. Rahman, "Fringe field and quantum mechanical effects on capacitance characteristics of sub-0.1 micron MOS devices," in Device Research Conference, 2003, June 23-25, 2003, pp. 53–54 [13] Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices Cambridge, U.K.: Cambridge Univ. Press, 1998. [14] C.-H. Choi, P. R. Chidambaram, R. Khamankar, C. F. Machala, Z. Yu, and R. W. Dutton, “Gate length dependent polysilicon depletion effects,” IEEE Electron Device Lett., vol. 56, pp. 224-226, Apr. 2002. [15] R. Degraeve, G. Groeseneken, R. Bellens, J. L. Ogier, M. Depas, P. J. Roussel, and H. E. Maes, “New insights in the relation between electron trap generation and the statistical properties of oxide breakdown,” IEEE Trans. Electron Devices. vol. 45, pp. 904-911, Apr. 1998. [16] J. H. Stathis and D. J. DiMaria, “Reliability projection for ultra-thin oxides at low voltage,” in IEDM Tech. Dig., 1998, pp. 167-170. [17] D. J. Dumin, J. R. Maddux, R. S. Scott, and R. Subramoniam, “A model relating wearout to breakdown in thin oxides,” IEEE Trans. Electron. Devices, vol. 41, pp. 1570–1580, Sept. 1994. [18] S. Inaba, K. Okano, and S Matsuda, “High Performance 35 nm Gate Length CMOS with NO Oxynitride Gate Dielectric and Ni Salicide” IEEE Transaction on Electron Device, vol. 49, NO. 12, pp. 2263-2270, Dec. 2002. [19] Technology and Manufacturing Group, Intel Corporation,” Transistor Elements for 30nm Physical Gate Lengths and Beyond”, Intel Technology Journal, vol. 06 Issue 02 Published, May, 2002 [20] G. J. Hu and R. H. Bruce, “Design tradeoffs between surface and buriedchannel FETs,” IEEE Trans. Electron Devices, vol. 32, pp. 584–588, Feb. 1985. [21] M. Cao, P. V. Voorde, M. Cox, and W. Greene, “Boron diffusion and penetration in ultrathin oxide with poly-Si gate,” IEEE Electron Devices Lett., vol. 19, pp. 291–293, Aug. 1998. [22] R. B. Fair, “Anomalous B penetration through ultrathin gate oxides during rapid thermal annealing,” IEEE Electron Devices Lett., vol. 20, pp. 466–469, Sept. 1999. [23] S. Inaba, K. Okano, and S. Matsuda, “High Performance 35 nm Gate Length CMOS with NO Oxynitride Gate Dielectric and Ni Salicide” IEEE Transaction on Electron Devices, vol. 49, NO. 12, pp. 2263-2269, Dec. 2002. [24] T.-M. Pan and T.-F. Lei, “Characterization of Ultrathin Oxynitride (18–21 Å) Gate Dielectrics by NH3 Nitridation and N2O RTA Treatment.” IEEE Transaction on Electron devices, vol. 48, NO. 5, pp.907-912, May 2001. [25] W. Vandervorst, B. Brijs, H. Bender, O. T. Conard, J. Petry, O. Richard, S. Van Elshocht, A. Delabie, M. Caymax, S. De Gendt, V. Cosnier, M. Green, and J. Chen, ”Physical characterization of ultrathin high k dielectrics” Plasma- and Process-Induced Damage, 2003 8th International Symposium, pp. 40–50, 24-25 Apr. 2003. [26] W.-H. Lin, K.-L. Pey, and Z. Dong, “Effects of Post-Deposition Anneal on the Electrical Properties of Si3N4 Gate Dielectric”, IEEE Electron Device Letters, vol. 23, NO. 3, pp. 124-126, Mar. 2002. [27] C-H Chen, Y-K Fang, and C-W Yang,” To Optimize Electrical Properties of the Ultrathin (1.6 nm) Nitride/Oxide Gate Stacks With Bottom Oxide Materials and Post-Deposition Treatment”, IEEE Transaction on Electron Devices, vol. 48, NO. 12, pp. 2769-2776, Dec. 2001. [28] Q. Xu, H. Qian, Z. Han, G. Lin, M. Liu, B. Chen, C. Zhu, and D. Wu, “Characterization of 1.9- and 1.4-nm Ultrathin Gate Oxynitride by Oxidation of Nitrogen-implanted Silicon Substrate,” IEEE Trans. on Electron Devices, vol. 51, NO. 1, pp. 113-120, Jan. 2004. [29] T.-M. Pan and T.-F. Lei, “Characterization of Ultrathin Oxynitride (18–21 Å) Gate Dielectrics by NH3 Nitridation and N2O RTA Treatment.” IEEE Transaction on Electron Devices, vol. 48, NO. 5, pp. 907-912, May 2001. [30] S. Peters, J. Y. Lee, and C. Ballif; “Rapid thermal processing: a comprehensive classification of silicon materials”, Photovoltaic Specialists Conference, 2002. Conference Record of the Twenty-Ninth IEEE, pp. 214 -217, 2002. [31] Q. Lu, Y.-C. Yeo, and K. J. Yang, “Two Silicon Nitride Technologies for Post-SiO2 MOSFET Gate Dielectric”, IEEE Electron Device Letters, vol. 22, NO. 7, pp. 324-326, July 2001. [32] I. Polishchuk, Q. Lu, and Y.-C. Yeo, “Intrinsic Reliability Projections for a Thin JVD,” IEEE Transaction on Electron Devices, vol.1, NO. 1, pp. 4-8, Mar. 2001. [33] L. S. Adam, C. Bowen, and M. E. Law, “On Implant-Based Multiple Gate Oxide Schemes for System-on-Chip Integration”, IEEE Transaction on Electron Devices, vol. 50, NO. 3, pp 589-600, Mar. 2004. [34] Y. Wu and G. Lucovsky, “Ultrathin nitride/oxide (N/O) gate dielectrics for p+-polysilicon gated PMOSFETs prepared by a combined remote plasma enhanced CVD/thermal oxidation process.” IEEE Electron Device Lett., vol 19, pp. 367-369, Oct. 1998. [35] I.C. Kizilyalli, R. Y. S. Huang, and R. K. Roy, “MOS transistors with stacked SiO2-Ta2O5-SiO2 gate dielectrics for giga-scale integration of CMOS technologies,” IEEE Electron Device Lett., vol. 19, pp. 423-425, Nov. 1998. [36] D. Park, Y.-C. King, Q. Lu, T.-J. King, C. Hu, A. Kalnitsky, S.-P. Tay, and C.-C. Cheng, “Transistor characteristics with Ta2O5 gate dielectric,” IEEE Electron Device Lett., vol. 19, pp. 441-443, Nov. 1998. [37] R. B. van Dover, and L. F. Schneemeyer, “Deposition of uniform Zr-Sn-Ti-O films by on-axis reactive sputtering,” IEEE Electron Device Lett., vol. 19, pp. 329-331, Sep. 1998. [38] K. N. ManjulaRani, V. Ramgopal Rao, and J. Vasi, “Reliability of ultrathin JVD silicon nitride MNSFETs under high field stressing,” in IPFA 2003, Proceedings of the 10th International Symposium on the 7-11 July 2003, pp. 168-172 [39] R. B. Fair, “Unified model of boron diffusion in thin gate oxides: effects of F, H2, N, oxide thickness and injected Si interstitials,” in IEDM Tech. Dig., 1995, pp. 85-88. [40] K. N. ManjulaRani, V. Ramgopal Rao, and J. Vasi, “Reliability of ultrathin JVD silicon nitride MNSFETs under high field stressing,” in IPFA 2003, Proceedings of the 10th International Symposium on the 7-11 July 2003, pp. 168-172 [41] X. W. Wang et al., “Highly reliable silicon nitride films made by jet vapor deposition,” Jpn. J. Appl. Phys., pt. 1, vol. 34, pp. 955–958, 1995. [42] M. Khare, X. W. Wang, and T. P. Ma, “Highly robust ultra-thin gate dielectric for giga scale technology,” in Symp. VLSI Technol. Dig. Tech Papers, 1998, pp. 218–219. [43] Q. Xu, H. Qian, Z. Han, G. Lin, M. Liu, B. Chen, C. Zhu, and D. Wu, “Characterization of 1.9- and 1.4-nm Ultrathin Gate Oxynitride by Oxidation of Nitrogen-implanted Silicon Substrate,” IEEE Trans. on Electron Devices, vol. 51, NO. 1, pp. 113-120, Jan. 2004. [44] M. R. Mirabedini, A. Kamath, and W. C. Yeh, “A study of nitrogen peak location in gate oxides grown on nitrogen implanted substrates and its impact on boron penetration,” IEEE Electron Device Lett., vol 24, pp. 301-303, May 2003. [45] Shimpei Tsujikawa, Toshiyuki Mine, Yasuhiro Shimamoto, Osamu Tonomura, Ryuta Tsuchiya, Kazuhiro Ohnishi, Hirotaka Hamamura, Kazuyoshi Torii, Takahiro Onai, and Jiro Yugami, “An ultra-thin silicon nitride gate dielectric with oxygen-enriched interface (OI-SiN) for CMOS with EOT of 0.9 nm and beyond,” Symp. on VLSI Tech., pp. 202-203, June 2002. [46] S. F. Ting, Y. K. Fang, C. H. Chen, C. W. Yang, W. T. Hsieh, J. J. Ho, M. C. Yu, S. M. Jang, C. H. Yu, M. S. Liang, S. Chen, and R. Shih, “The effect of remote plasma nitridation on the integrity of the ultrathin gate dielectric films in 0.13 m CMOS technology and beyond,” IEEE Electron Device Lett., vol. 22, pp. 327–329, 2001. [47] C. H. Chen, Y. K. Fang, C.W. Yang, S. F. Ting, Y. S. Tsair, M. F.Wang, Y. M. Lin, M. C. Yu, S. C. Chen, C. H. Yu, and M. S. Liang, “Highquality ultrathin (1.6 nm) nitride/oxide stack gate dielectrics prepared by combining remote plasma nitridation and LPCVD technologies,” IEEE Electron Device Lett., vol. 22, pp. 260–262, June 2001. [48] G. D. Wilk and B. Brar, “Electrical Characteristics of High-Quality Sub-25-Å Oxides Grown by Ultraviolet Ozone Exposure at Low Temperature,” IEEE Electron Device Lett., vol. 20, pp. 132–134, Mar. 1999. [49] M. Goryll, J. Moers, St. Trellenkamp, L. Vescan, M. Marso, P. Kordos, H. Luth, “Thin low-temperature gate oxides for vertical field-effect transistors,” on Advanced Semiconductor Devices and Microsystems, 2002, The Fourth International Conference on , 14-16 Oct. 2002, pp. 275–277.
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