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研究生:王信文
研究生(外文):Hsin-Wen Wang
論文名稱:具自我校正功能之全數位3GbpsSATA驅動電路設計
論文名稱(外文):A Self-Calibrate All-Digital 3Gbps SATA Driver Design
指導教授:蘇朝琴
指導教授(外文):Chau-Chin Su
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電機與控制工程系所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2004
畢業學年度:92
語文別:英文
論文頁數:70
中文關鍵詞:高速串列鏈結低電壓差動訊號標準同步切換雜訊抑制自我校正
外文關鍵詞:High-speed serial linkLVDSSSN-reductionSelf-Calibrate
相關次數:
  • 被引用被引用:1
  • 點閱點閱:229
  • 評分評分:
  • 下載下載:1
  • 收藏至我的研究室書目清單書目收藏:0
由於製程技術的進步,CMOS積體電路的操作頻率及電路複雜度也隨著增加。使得晶片內部的邏輯閘以及連結外部的輸入/輸出介面之間的頻寬差距到達嚴重的比例。因此,連接晶片之間的傳輸通道時常限制了系統的效能,這些系統包括網路的切換器、路由器、處理器和記憶體之間的介面及多處理器的傳輸通道。
在此論文中,我們有兩個研究主題。首先,我們將簡單的討論及計算介面電路的雜訊來源以及印刷電路版的知識。依據這些知識,我們提出一個可抑制同步切換雜訊且符合低電壓差動訊號標準的2.5 Gbps傳送器。接著,我們再提出一個有自我校正功能,可應用於第二代SATA的驅動電路。使用此技術的傳輸器將可工作在3 Gbps的位元傳輸率,並可以對輸出電壓準位做自動的調整,以防止製程漂移或溫度變化而造成輸出準位的誤差,實現此傳輸器的電路技術及設計概念也將再論文中說明。
論文中,我們將實現一個符合低電壓差動訊號標準2.5 Gbps的傳送器。此傳送器是使用0.18μm的製程製作且在1.8V的供應電壓下可以操作在2.5 Gbps,另外晶片面積則為 。使此設計能工作在2.5 Gbps的技術包括使用點對點的傳輸,並加入我們所提出抑制同步切換雜訊的機制。
Due to process technologies scale-down, the operating frequency and circuit complexity of CMOS VLSI increase. The growing gap between on-chip gates and off-chip I/O bandwidth is reaching the critical proportions. Therefore, the interconnections between chips often limit the performance of a system in application such as network switches, routers, processor-memory interfaces, and multi-processor interconnection. For this reason, to integrate high speed serial links on chips can reduce the pin/wire count, and power budget of a system significantly.
There are two major topics in this thesis. First, we will focus on the study of signaling noise sources and channel (PCB) modeling. Base on these considerations, we will propose the 2.5 Gbps transmitter that conforms to the Low Voltage Differential Signal (LVDS) specifications and Simultaneous switching noise (SSN) reduction. Second, we will propose a driver circuit design which can auto calibration itself and apply to second generation SATA. So the driver can prevent the output voltage error from process or temperature variation. This transmitter for the physical layer of a serial link will have a data bandwidth of 3 Gbps. The circuit design and operational concept for the transmitter will be described in the thesis.
In this thesis, a 2.5 Gbps transmitter has been implemented. It is compatible with the LVDS standard. In a TSMC 0.18-μm 1P6M CMOS technology, the transmitter circuit operates at 2.5 Gbps on a 1.8V power supply and occupies an area of . The technique to achieve 2.5 Gbps data rate is using point-to-point topology and the novel methodology that reduce the SSN.
Table of Contents
TABLE OF CONTENTS V
LISTS OF FIGURES VII
LISTS OF TABLES IX
CHAPTER 1 INTRODUCTION - 1 -
1.1 MOTIVATION - 1 -
1.2 CMOS SERIAL LINKS - 2 -
1.3 THESIS ORGANIZATION - 4 -
CHAPTER 2 BACKGROUND STUDY - 6 -
2.1 SIGNALING TECHNIQUES - 6 -
2.2 NOISE SOURCE - 8 -
2.3 CHANNEL ANALYSIS - 12 -
CHAPTER 3 2.5GBPS LVDS TRANSMITTER WITH SSN REDUCTION - 20 -
3.1 SIMULTANEOUS SWITCHING NOISE REJECTION - 20 -
3.2 TRANSMITTER ARCHITECTURE - 25 -
3.3 SYSTEM COMPONENTS - 27 -
3.4 TRANSMITTER SIMULATION - 34 -
3.5 SUMMARY - 42 -
CHAPTER 4 A SERIAL-ATA DRIVER WITH OUTPUT SELF-CALIBRATION - 43 -
4.1 MOTIVATION - 43 -
4.2 OVERALL ARCHITECTURE - 44 -
4.3 BUILDING BLOCKS - 45 -
4.4 SIMULATION RESULT - 50 -
4.5 TAPE OUT AND SUMMARY - 58 -
CHAPTER 5 MEASUREMENT RESULTS - 60 -
5.1 TAPE OUT - 60 -
CHAPTER 6 CONCLUSION - 66 -
6.1 CONCLUSION - 66 -
6.2 FUTURE WORK - 67 -
BIBLIOGRAPHY - 68 -
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