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研究生:莊英廷
研究生(外文):Ying-Ting Chuang
論文名稱:全數位2.5Gbps相位校正緩衝器設計
論文名稱(外文):All Digital 2.5Gbps Deskew Buffer Design
指導教授:蘇朝琴
指導教授(外文):Chau-Chin Su
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電機與控制工程系所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2004
畢業學年度:92
語文別:英文
論文頁數:49
中文關鍵詞:相位校正延遲線迴路
外文關鍵詞:deskewDLLdelay locked loop
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本論文描述一個利用數位方式來使得資料和時脈同步化的相位校正緩衝器。資料頻率定於625Mbps和2.5Gbps。
為了避免資料在被序列化時發生錯誤,傳送端必須要做的第一件事是解決資料和時脈之間的相位差。相位校正緩衝器的基本概念和延遲線迴路相同,主要的目的都是要調整相位當有相位差時。全數位的相位校正緩衝器不僅可以有較低的功率消耗且更容易地重覆使用和實現。此設計採用0.18μm 1P6M TSMC CMOS製程技術實現。相位校正器在625Mbps的資料輸出經過時序調整後的抖動值為48ps,消耗功率為3.8毫瓦。而在2.5Gbps的資料輸出經過時序調整後的抖動值為26.5ps,消耗功率為16毫瓦。
CONTENTS

ABSTRACT (CHINESE) i
ABSTRACT (ENGLISH) ii
ACKNOWLEDGEMENT iii
CONTENTS v
LIST OF TABLES vii
LIST OF FIGURES viii

CHAPTER 1 INTRODUCTION
1.1 MOTIVATION 1
1.2 THESIS ORGANIZATION 3
CHAPTER 2 BACKGROUND
2.1 BASIC SERIAL LINK 4
2.2 DELAY-LOCKED LOOP (DLL) 7
2.2.1 INTRODUCTION OF CONVENTIONAL DLL 7
2.2.2 INTRODUCTION OF DIGITAL DLL 9
2.2.3 SURVEY OF ANALOG DLL 10
2.2.4 SURVEY OF DIGITAL DLL 13
CHAPTER 3 625MBPS DESKEW BUFFER
3.1 OVERVIEW OF DESKEW BUFFER 15
3.2 ARCHITECTURE OF DESKEW BUFFER 16
3.3 PHASE DETECTOR 17
3.4 CONFIDENCE COUNTER 19
3.5 PHASE SELECTOR 21
3.6 DIGITAL CONTROL DELAY LINE 23
3.7 625MBPS DESKEW BUFFER SIMULATION RESULT 24
3.7.1 SIMULATION OF DCDL 25
3.7.2 SIMULATION OF DESKEW BUFFER 25
3.8 2.5GBPS DESKEW BUFFER 28
3.8.1 ARCHITECTURE OF DESKEW BUFFER 28
3.8.2 SIMULATION OF 2.5GBPS DESKEW BUFFER 31
3.9 RESEARCH IN CONFIDENCE COUNTER 35
CHAPTER 4 EXPERIMENTAL RESULTS
4.1 EXPERIMENT SETUP 38
4.2 PRINT CIRCUIT BOARD LAYOUT 38
4.3 EXPERIMENTAL RESULTS 40
CHAPTER 5 CONCLUSIONS
5.1 CONCLUSIONS 47
REFERENCES 48
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[2] J.G. Proakis, “Digital Communications,” McGraw-Hill High Education, 2001
[3] Yongquan Fan, Zeljko, Z, Man Wah Chiang, “A versatile high speed bit error rate testing scheme”, Quality Electronic Design, 2004. Proceedings. 5th International Symposium on, Pages:395 – 40, 22-24 , March 2004
[4] Johnson, M.G., Hudson, E.L, “A variable delay line PLL for CPU-coprocessor synchronization” IEEE Journal of Solid-State Circuits, Volume: 23, Pages:1218 - 1223 , Oct. 1988
[5] Efendovich, A.; Afek, Y., Sella, C., Bikowsky, Z., “Multifrequency zero-jitter delay-locked loop” IEEE Journal of Solid-State Circuits, Volume: 29, Pages:67 - 70 , Jan 1994
[6] Garlepp, B.W., Donnelly, K.S., Jun Kim, Chau, P.S., Zerbe, J.L., Huang, C., Tran, C.V.; Portmann, C.L., Stark, D., Yiu-Fai Chan, Lee, T.H., Horowitz, M.A., “A portable digital DLL for high-speed CMOS interface circuits” IEEE Journal of Solid-State Circuits, Volume: 34, Pages:632 - 644 , May 1999
[7] Yongsam Moon, Jongsang Choi, Kyeongho Lee, Deog-Kyoon Jeong, Min-Kyu Kim, “An all-analog multiphase delay-locked loop using a replica delay line for wide-range operation and low-jitter performances” IEEE Journal of Solid-State Circuits, Volume: 35, Pages:337 - 384 , March 2000
[8] Hai Tao; Shaeffer, D.K., Min Xu; Benyamin, S., Condito, V., Kudszus, S., Qinghung Lee, Ong, A., Shahani, A., Xiaomin Si, Wong, W., Tarsia, M., “40-43-Gb/s OC-768 16:1 MUX/CMU chipset with SFI-5 compliance”, Solid-State Circuits, IEEE Journal of , Volume: 38 , Pages:2169 – 2180 , Dec. 2003
[9] Shen-Iuan Liu; Jiunn-Hwa Lee; Hen-Wai Tsao;” Low-power clock-deskew buffer for high-speed digital circuits”, Solid-State Circuits, IEEE Journal of , Volume: 34 , Pages:554 – 558, April 1999
[10] C.K. Ken Yang ,“Design of High-Speed Serial Links in CMOS,” Ph.D. Dissertation, Stanford University, 1998.
[11] Ching-Che Chung, Chen-Yi Lee, “An All-Digital Phase-Locked Loop for High-Speed Clock Generation “ , Solid-State Circuits, IEEE Journal of , Volume: 38 , Pages:347 - 351 , Feb. 2003
[12] Behzad Razavi, “Design of Integrated Circuits for Optical Communications, “McGraw Hill, 2002.
[13] Neil H. E. Weste, Kamran Eshraghian, “Principles of CMOS VLSI design, second edition” Addison Wesley.
[14] Behzad Razavi, “Design of analog CMOS integrated circuits” McGraw-Hill international edition.
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