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研究生:蔡文洲
研究生(外文):Wen-Chou Tsai
論文名稱:矽鍺異質源/汲極結構與pn二極體之研製
論文名稱(外文):Study and Processing of Hetero-SiGe/Si S/D Structure and P-N Diode
指導教授:李佩雯李佩雯引用關係
指導教授(外文):Pei-Wen Li
學位類別:碩士
校院名稱:國立中央大學
系所名稱:電機工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2004
畢業學年度:92
語文別:中文
論文頁數:104
中文關鍵詞:超淺接面源/汲極結構高溫濕氧化異質矽鍺/矽pn二極體嵌入式/提升式異質矽鍺/矽pn二極體開啟電壓理想因數逆向飽和電流崩潰電壓金氧
外文關鍵詞:short-channel-effectbreakdown voltagejunction capacitancereverse saturation currentideality factorturn on voltageshallow junction S/D structurewet oxidationhetero-SiGe/Si P-N dioderecessed/raised P-N diode
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摘要
在本論文中,利用ICP與smart-EPDTM製作出超淺接面源/汲極結構,並且搭配高溫濕氧化(wet oxidation)將受損的表面氧化後,由氫氟酸水溶液將氧化後的缺陷層移除,完成淺接面源/汲極結構的製作。
本論文的另一重點為異質矽鍺/矽pn二極體的製作。利用LPCVD成長複晶矽鍺材料並以黃光設備搭配電漿蝕刻回蝕刻技術將pn二極體圖形定義出來,完成製作嵌入式/提升式異質矽鍺/矽pn二極體。而在元件直流特性上,嵌入式異質矽鍺/矽pn二極體無論是在開啟電壓(Von)、理想因數(n)、逆向飽和電流(Isat)與崩潰電壓(Vbd)有較佳的特性表現,同時也展現此異質結構較不易受鍺含量多寡的限制以及有效的抑制短通道效應,具實現高速與低功率消耗的元件設計之潛能。
運用嵌入式異質矽鍺/矽結構於MOSFETs的源/汲極上將可壓縮短通道效應,實現未來奈米金氧半電晶體發展之趨勢。因此,嵌入式矽鍺源極/汲極結構的確是一個適合運用於尺寸小、速度快與消耗功率低的奈米電子元件。
Abstract
In this thesis, we fabricated shallow junction S/D structure by ICP and smart-EPDTM. We applied high temperature wet oxidation to oxidize the defective surface. The oxidized defective layer was then removed by hydrofluoric (HF) acid.
We also fabricated hetero-SiGe/Si P-N diode. We first grew poly-SiGe material by LPCVD. The recessed/raised P-N diode was then patterned by yellow light equipments and plasma-etching-back techniques. As for DC characteristics, the recessed P-N diode performs better in turn on voltage (Von), ideality factor (n), reverse saturation current (Isat), junction capacitance (Cj), and breakdown voltage (Vbd). We also show that the recessed heterostructure is less dependent on the Ge content and effectively suppresses short-channel-effect. Therefore, the recessed hetero-SiGe/Si P-N diode is one of the best candidates to realize high speed and low power consumption.
By incorporating recessed hetero-SiGe/Si structure into the S/D of MOSFETs, we can compress short-channel-effect, and thus continue the scaling trend of MOSFETs into the nano-scale region. Therefore, recessed SiGe/Si S/D structure can realize nano-scale electronic devices with high speed and low power consumption.
目錄
摘要…………………………………………….……………………….Ⅰ
致謝……………………………………………………………………..Ⅱ
圖目錄…………………………………………………………………..Ⅲ
表目錄…………………………………………………………………..Ⅸ
序章 論文結構介紹…………………………………………………..Ⅹ

第一章 介紹……………………………………………………………..1
1-1 前言…………………………………………………………….1
1-2 研究動機……………………………………………………….1
1-3 研究目的與應用……………………………………………….5

第二章 矽鍺異質結構在金氧半電晶體之可能應用…………………13
2-1 前言…………………………………………………………...13
2-2 異質接面矽鍺/矽材料特性之簡述…………………………..14
2-3 矽鍺源/汲極結構之應用……………………………………..15
2-4 異質矽鍺源/汲極之可能形成方法與比較…………………..16
2-4-1 鍺離子佈植源/汲極結構………………………………..17
2-4-2 提升式矽鍺源/汲極結構………………………………..18
2-4-3 嵌入式矽鍺源/汲極結構………………………………..18
2-4-3.1 結構設計…………………………………………19
2-4-3.2 模擬結果與分析…………………………………19
2-5 結論…………………………………………………………...21

第三章 嵌入式異質矽鍺源/汲極結構之關鍵製程開發……………...35
3-1 前言…………………………………………………………...35
3-2 超淺接面源/汲極製程步驟…………………………………..35
3-2-1 乾式電漿蝕刻製程設備………………………………...36
3-2-1.1 蝕刻反應器………………………………………37
3-2-1.2 製程監督和終點偵測……………………………38
3-2-2 複晶矽閘極蝕刻………………………………………...39
3-2-3 間隙壁回蝕刻…………………………………………...43
3-2-4 源/汲極等向性蝕刻……………………………………..49
3-3 複晶矽鍺薄膜的成長……………………………….………..51
3-4 結論…………………………………………………………...52

第四章 異質矽鍺/矽pn二極體製程與量測分析……………………..71
4-1 前言…………………………………………………………...71
4-2 矽鍺/矽pn二極體製程步驟………………………………….71
4-3 pn接面二極體的電性特性…………………………………...73
4-4 電性量測……………………………………………………...76
4-4-1 邊際效應………………………………………………...77
4-4-2 順向偏壓與電流特性…………………………………...78
4-4-2.1 開啟電壓…………………………………………78
4-4-2.2 理想因數…………………………………………79
4-4-3逆向偏壓與電流特性…………………………………….80
4-4-3.1逆向飽和電流……………………………………..80
4-4-3.2崩潰電壓…………………………………………..81
4-4-3.3接面電容…………………………………………..83
4-5 結論…………………………………………………………...83

第五章 總結與未來展望……………………………………………....99

參考文獻資料…………………………………………………………101
參考文獻資料
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