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研究生:吳明峰
研究生(外文):Ming-Feng Wu
論文名稱:具倍頻電路1.5μs鎖定速度之2.4GHz鎖相迴路
論文名稱(外文):A 1.5 μs Lock-in Speed 2.4 GHz Phase-Locked Loop Designed Based on a Frequency-Double Circuit
指導教授:林志明林志明引用關係
指導教授(外文):Zhi-Ming Lin
學位類別:碩士
校院名稱:國立彰化師範大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2004
畢業學年度:92
語文別:英文
論文頁數:127
中文關鍵詞:鎖相迴路倍頻電路鎖定速度2.4 GHz
外文關鍵詞:PLLFrequency-Double circuitLock-in Speed2.4 GHz
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近年來,由於積體電路的技術蓬勃發展,可攜式的個人通訊器材普及,以及電腦時脈速度大幅提升的情況下,鎖相迴路再度受到重視。因此在單晶片系統(System On a Chip),鎖相迴路可說是熱門電路。隨著可攜式通訊器材的應用,高頻輸出以及鎖定時間便成為鎖相迴路的重要性能指標。
本論文提出一具倍頻電路且能快速鎖定之2.4 GHz鎖相迴路(PLL)設計。在相位頻率偵測器(PFD)部分,使用無任何回授路徑之三態輸出架構,具有低相位誤差、低動態消耗功率以及低鎖定時間之特性。在充電浦(CP)部分,則使用差動架構,能有效地對電容充電或放電,降低無輸出的輸入範圍(dead-zone)。在電壓控制振盪器(VCO)部分,使用差動型式的設計,可有效增加可調頻率範圍且具溫度補償的效果。倍頻電路的設計基於橋式整流的型式,可以產生兩倍於輸入頻率的輸出訊號。當工作電壓為3.3 V且輸入外部頻率為37.5 MHz時,使用TSMC 0.35 μm 2P4M CMOS製程技術下,此鎖相迴路產生1.2 GHz的振盪頻率,系統無輸出的輸入範圍為10ps,鎖定時間為1.5μs,和1 MHz位移的-98 dBc/Hz相位誤差。當振盪頻率經由倍頻電路產生輸出頻率為2.4 GHz時系統平均消耗功率約為7.65 mW。

Recently, with the progress of VLSI technology, Phase-Locked Loop (PLL) is broadly used in mobile communication system and clock recovery of computer system. Owing to the use of mobile communication system, high frequency and locked time have become the main concern in design of the modern PLL.
This thesis proposed a rapid acquisition phase-locked loop and frequency-double circuit for 2.4 GHz frequency band. The phase frequency detector is designed with three-state output without any feedback paths. The charge pump is implemented by using a differential structure to reduce the dead-zone effectively. The voltage-controlled oscillator is designed to increase tuning range with temperature-stable scheme. The frequency-double circuit is based on a bridge rectification type and generates a duplicate output frequency in 2.4 GHz. With a 3.3 V supply voltage and 37.5 MHz reference frequency, the PLL attains 1.2 GHz oscillation frequency, 10 ps dead-zone, 1.5 μs locked time, and -98 dBc/Hz at 1 MHz offset as simulated in TSMC 0.35μm 2P4M CMOS technology. The frequency-double circuit duplicates the oscillation frequency, where 2.4 GHz. output. The average power consumption of overall architecture is about 7.65 mW.
摘要………………………………………………………………………………....i
ABSTRACT………………………………………………………………………..ii
誌謝……………………………………………………………………………….iii
TABLE OF CONTENTS……………………………………………………….....iv

LIST OF FIGURES………………………………………………………………..vi
LIST OF TABLES……………………………………………………………….....x

CHAPTER 1 INTRODUCTION …………………………...………...………....1
1.1 Motivation………………………………………………………..1
1.2 Phase-Locked Loop Architecture………………………………...3
1.3 Thesis Overview……………………………………………….4
CHAPTER 2 THE BASICS OF PHASE-LOCKED LOOP…………….………5
2.1 Phase-Locked Loop (PLL) Fundamentals…………………….. 5
2.2 Linear Model of Charge Pump Phase-Locked Loop……………14
CHAPTER 3 VOLTAGE-CONTROLLED OSCILLATOR AND
FREQUENCY-DOUBLE CIRCUIT…………………………….19
3.1 Preliminary of Voltage-Controlled Oscillator(VCO)…………....19
3.2 Design of the Proposed Voltage-Controlled Oscillator………....26
3.3 Design of Frequency-Double Circuit…………………………..36
3.4 Noise Analysis of VCO and Frequency-Double Circuit………50
CHAPTER 4 PHASE FREQUENCY DETECTOR, CHARGE PUMP AND
FREQUENCY DIVIDER……………...…...................................56
4.1 Principle of Phase Frequency Detector……………..……..….. 56
4.2 Design of Phase Frequency Detector…………………………... 61
4.3 Principle of Charge Pump……………………………………….69
4.4 Design of Charge Pump……………………………………….73
4.5 Design of Frequency Divider………………………………….78
CHAPTER 5 LOOP FILTER AND CLOSED-LOOP PERFORMANCE……...84
5.1 Fundamentals of Loop Filter…………………..………………84
5.2 Design of Loop Filter………………………………..…………85
5.3 Closed-Loop Performance………………………..……………93
CHAPTER 6 CONCLUSIONS……………………………..…………….…100
REFERENCES……………………………………………………….…...........102
APPENDIX A……………………………………………………………….…..106
APPENDIX B……………………………………………………………….…...113

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