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研究生:周建平
研究生(外文):Chien-Ping Chou
論文名稱:應用於多相位頻率合成器之波形轉換器
論文名稱(外文):A Delay-Locked Loop Based Waveform Converter for Multiphase Frequency Synthesizer
指導教授:林志明林志明引用關係
指導教授(外文):Zhi-Ming Lin
學位類別:碩士
校院名稱:國立彰化師範大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2004
畢業學年度:92
語文別:英文
論文頁數:67
中文關鍵詞:波形轉換器相位偵測器充電浦電壓控制延遲線
外文關鍵詞:Waveform ConverterPhase DetectorCharge PumpVoltage-Controlled Delay Line
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這篇論文提出一個波形轉換器,它是設計在0.35μm CMOS 的製程且使用3 V的供應電壓。這個波形轉換器會轉換一個矩形波訊號而來產生相位相差90°的I/Q弦波訊號, 而這兩個輸出的弦波訊號非常適用於頻率合成器(Frequency Synthesizer)或是收發器(Transceiver)中的混波器(Mixer)。波形轉換器的兩個輸出頻率可以提供輸入訊號的N倍頻率。這個波形轉換器是建構在延遲栓鎖迴路(Delay-Locked Loop)上其會有較低的相位雜訊(Phase noise)及較寬的輸出頻率範圍,其相位偵測器(PD)在設計上使用三態輸出,使整體的消耗功率有效的降低。在充電浦(Charge Pump)部份,是使用單端可變型式且使用電流控制開關的架構,可以在對電容充放電時, 能有效的降低其相位誤差,而因此降低其無輸出之輸入範圍(Dead-Zone)。而電壓控制延遲電路(Voltage-Controlled Delay Line)是最主要控制輸出頻率的地方,在設計上用源極控制來降低電路的延遲時間,能使輸出的頻率更高。本篇所提出的波形轉換器的頻率輸出範圍從485MHz 到3.02GHz當電路在2GHz的時候,其相位雜訊(Phase noise)在10 kHz偏差時為-130.1 dBc/Hz,其功率消耗為4.287 mW。
This paper proposes a waveform converter, designed in 0.35-μm CMOS process with 3-V supply voltage. The waveform converter converts a square wave signal to produce in-phase and quadrature-phase sinusoidal signal outputs. The two output signals are suitable to be applied in the design of frequency synthesizer and mixer of transceiver. The output frequency of waveform converter can provide N-multiplication frequency of the input frequency. The waveform converter structure has lower phase noise and wider output frequency range based on a delay-locked loop (DLL). The phase detector (PD) of the DLL uses three-output state to reduce power consumption of waveform converter effectively. The charge pump (CP) of the DLL is a variation with current steering switch. When the charging and discharging to capacitor is symmetric, the phase error can be reduced effectively and thus is able to reduce the dead-zone of the DLL. The voltage-controlled delay line (VCDL) is mainly controlling the output frequency. We control the source voltage to reduce the delay time of the VCDL and thus increase the output frequency. The output frequency of this waveform converter is ranging from 485 MHz to 3.02 GHz. The phase noise at 10-kHz offset from the carrier is –130.1 dBc/Hz. The power consumption is 4.287 mW at 2 GHz.
摘要 …………………………………………………………………………….i
ABSTRACT. ………………………………………………………………ii
誌謝 ……………………...…………………………………………………....iii
TABLE OF CONTENTS ….….……….……………………………………iv
LIST OF FIGURES. …………………………………………………………vi
LIST OF TABLES ……………………………………………………………ix

CHAPTER 1 INTRODUCTION …………………………………………….1
1.1 Research Background and Motivation…………………………...1
1.3 Outline of the Thesis…………….……………………………3
CHAPTER 2 WAVEFORM CONVERTER……………………………...4
2.1 Principles of Waveform Converter…………………………….4
2.2 Reported Waveform Converter…………………………….5
2.3 The Designed Waveform Converter…………………………7
CHAPTER 3 DELAY-LOCKED LOOP……………………………….15
3.1 Introduction of Delay-Locked Loop………………………….15
3.2 Analysis of the Charge Pump Delay-Locked Loop…………16
3.3 Linear Model of Delay-Locked Loop………………….……….18
3.4 The proposed Delay-Locked Loop ……………………………23
CHAPTER 4 PHASE DETECTOR ……………………………………….26
4.1 Principle and Characteristic of Phase Detector………………….26
4.2 Previous Architectures of Phase Detector……………………….30
4.3 The Proposed dec-PD Architecture……………………….…….32
CHAPTER 5 CHARGE PUMP AND VOLTAGE-CONTROLLED DELAY LINE …………………………...……………….………………….40
5.1 Overview of Charge Pump ………………………………….40
5.2 Non-ideal Effect of Charge Pump……………………………….41
5.3 Design of the Charge Pump…………………………………43
5.4 Design of Voltage-Controlled Delay Line………………….47
CHAPTER 6 SIMULATION RESULT AND ANALYSIS………………51
CHAPTER 7 CONCLUSIONS……………………………………………61
REFERENCES……………………………………………………………...62
APPENDIX ………………………………………………………………….66


[1] J. Craninckx and M. J. Steaert, “A 1.8-GHz low-phase-noise CMOS VCO using optimised hollow spiral inductors,” IEEE J. Solid-State Circuits, vol. 32, pp. 736-744, May 1997.
[2] G. Chien and P. R. Gray, “A 900 MHz local oscillator using a DLL-based frequency multiplier technique for PCS applications,” in Proc. of IEEE Int. Solid-State Circuit Conf. Dig. Tech,. Feb. 2000, pp. 202-203.
[3] A. Spataro, Y. Deval, J.-B Begueret, P. Fouillat, and D. Belot, , “A VLSI CMOS delay oriented waveform converter for polyphase frequency synthesizer,” IEEE J. Solid-State Circuits, vol. 37, pp. 336-341, March 2002.
[4] Sung-Sik Hwang, Ki-Mo Joo, Ho-Jin Park, Jae-Whui Kim, and Chung, P., “A DLL based 10-320 MHz clock synchronizer,” in Proc. of the 2000 IEEE International Symposium on Circuits and Systems, vol. 5, May 2000, pp. 265-268.
[5] A.Spataro, Y. Deval, J.B. Begueret, and P. Fouillat, “Delay oriented design methodology: application to the design of a VHF low power VLSI polyphase oscillator,” in Proc. of the 7th IEEE International Conference on Electronics, Circuits and Systems, vol. 1, Dec. 2000, pp. 248-251.
[6] A. Hajimiri, S. Limotyakis, and T. H. Lee, “Jitter and phase noise in ring oscillators,” IEEE Journal of Solid-State Circuits, vol. 34, pp. 790-804, June 1999.
[7] Kuo-Hsing Cheng, Yu-Lung Lo, and Wen-Fang Yu, “A Mixed-Mode Delay-Locked Loop for Wide-Range Operation and Multiphase Outputs,” in Proceedings of the 2003 International Symposium on Circuits and Systems, vol. 2, May 2003, pp. 196 –199.
[8] Takanori Saeki, et al., “A 2.5-ns Clock Access, 250-MHz, 256-Mb SDRAM with Synchronous Mirror Delay,” IEEE J. Solid-State Circuits, vol. 31, pp. 1658-1668, Nov. 1996.
[9] Takanori Saeki, Koichiro Minami, Hiroshi Yoshida, and Hisamitsu Suzuki, “A Direct-Skew Detect Synchronous Mirror Delay for Application-Specific Integrated Circuits,” in Proc. of the IEEE Custom Integrated Circuits Conference, 1998, pp. 511-514.
[10] M. Mota and J. Christiansen, “A high-resolution time interpolator based on a delay locked loop and an RC delay line,” IEEE J. Solid-State Circuits, vol. 34, no. 10, pp. 1360-1366, Oct. 1990.
[11] A. Hatakeyama, et al., “A 256-Mb SDRAM using a register-controlled digital DLL,” IEEE J. Solid-State Circuits, vol. 32, pp. 1728-1734, Nov.1997.
[12] Behzad Razavi, Design of Analog CMOS Integrated Circuits. McGraw-Hill, 2001.
[13] A. Spataro, Y. Deval, J.B. Begueret, and P. Fouillat, “Delay oriented design methodology: application to the design of a VHF low power VLSI polyphase oscillator,” in Proc. of the 7th IEEE International Conference on Electronics, Circuits and Systems, vol. 1, Dec. 2000, pp. 248-251.
[14] A. Hajimiri, S. Limotyakis, and T. H. Lee, “Jitter and phase noise in ring oscillators,” IEEE Journal of Solid-State Circuits, vol. 34, pp. 790-804, Jane 1999.
[15] Kuo-Hsing Cheng, Yu-Lung Lo, and Wen-Fang Yu, “A Mixed-Mode Delay-Locked Loop for Wide-Range Operation and Multiphase Outputs,” in Proceedings of the 2003 International Symposium on Circuits and Systems, vol. 2, May 2003, pp. 196 –199.
[16] R. E. Best, Phase-Locked Loops. 2nd Ed. McGraw-Hill, 1993.
[17] H. O. Johansson, “A Simple Precharged CMOS Phase Frequency Detector,” IEEE J. of Solid-State Circuits, vol. 33, no. 2, pp. 295-299, Feb. 1998.
[18] P. Larsson and C. Svensson, “Skew safety and logic flexibility in a true single phase clocked system,” in Proc. of IEEE Int. Symp. Circuits Syst., vol 2, May 1995, pp. 941-944.
[19] K. H. Cheng, T. H. Yao, S. Y. Jiang and W. B. Yang, “A Difference Detector PFD for Low Jitter PLL,” in Proceeding of the 8th IEEE Int. Conference on Circuits and Systems, vol. 1, Sept. 2001, pp. 43-46.
[20] Rola A. Baki and Mourad N. El-Gamal, “A New CMOS Charge Pump for Low-Voltage (1V) High-Speed PLL Applications,” in Proceedings of the 2003 International Symposium on Circuits and Systems, vol. 1, pp. 657-660, May 2003.
[21] Jae-Shin Lee, Min-Sun Keel, Shin-Il Lim, and Suki Kim, “Charge Pump with Perfect Current Matching Characteristics in Phase-Locked Loops,” Electronics Letters, vol. 36, pp. 1907-1908, Nov. 2000.
[22] M. J.E.Lee, W.J. Dally, J.W. Poulton, P. Chiang, and S.E. Greenwood, “An 84-mW 4-Gb/s clock and data recovery circuit for serial link applications,” Digest of Technical Papers. 2001 Symposium on VLSI Circuits, June 2001, pp. 149-152.
[23] W. Rhee, “Design of High-Performance CMOS Charge Pumps in Phase-Locked Loops,” in Proceedings of the 1999 IEEE International Symposium on Circuits and Systems, vol. 2, June 1999, pp. 545-548.
[24] C. Olgaard, et al., “Apparatus for reducing power consumption of device controlled by counter and noise due to counter reload,” National Semiconductor Crop., Patent no. 3341.
[25] J.G. Maneatis, “Low-jitter process-independent DLL and PLL based on self-biased techniques,” IEEE Journal of Solid-State Circuits, vol. 31, pp. 1723-1732, Nov. 1996.
[26] Gyudong Kim, Min-Kyu Kim, Byoung-Soo Chang, and Wonchan Kim, “A low-voltage, low-power CMOS delay element,” IEEE Journal of Solid-State Circuits, vol. 31, pp. 966 –971, July 1996.
[27] Yongsam Moon, Jongsang Choi, Kyeongho Lee, Deog-Kyoon Jeong, and Min-Kyu Kim, “A 62.5-250 MHz multi-phase delay-locked loop using a replica delay line with triply controlled delay cells,” in Proceedings of the IEEE 1999 Custom Integrated Circuits, May 1999, pp. 299-302.
[28] A. Hajimiri, S. Limotyakis, and T. H. Lee, “Jitter and phase Noise in Ring Oscillators,” IEEE Journal of Solid-State Circuits, vol. 34, pp. 790-804, June 1999.
[29] Kuo-Hsing Cheng, Yu-Lung Lo, and Wen-Fang Yu, “A Mixed-Mode Delay-Locked Loop for Wide-Range Operation and Multiphase Outputs,” in Proceedings of the 2003 International Symposium on Circuits and Systems, vol. 2, pp. 196 –199, May 2003.
[30] A. Spataro, Y. Deval, J.-B. Begueret, P. Fouillat, and D. Belot, , “A VLSI CMOS delay oriented waveform converter for polyphase frequency synthesizer,” IEEE Journal of Solid-State Circuits, vol. 37, pp. 336- 341, March 2002.

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