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研究生:李崇漢
研究生(外文):Chung-Han Lee
論文名稱:多功能數位轉換之參數化IP產生器
論文名稱(外文):An IP Generator for Multifunctional Discrete Transforms using Parameterized Modules
指導教授:蕭勝夫
指導教授(外文):Shen-Fu Hsiao
學位類別:碩士
校院名稱:國立中山大學
系所名稱:資訊工程學系研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2004
畢業學年度:92
語文別:中文
論文頁數:62
中文關鍵詞:數位轉換參數化
外文關鍵詞:Parameterized ModulesDiscrete Transforms
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本論文中以N點數位轉換之快速演算法來實現移位式快速傅立葉轉換(SDFT),利用有效的矩陣分解來減少運算的複雜度,並將分解之矩陣分別映射到參數化的IP 模組上,再藉由串接這些IP模組,以實現各種類的數位轉換運算, 包括影像視訊壓縮常見的餘弦轉換(DCT)和音訊壓縮常見的 MDCT。由於各參數化的IP模組的規則性,可藉由改變參數,達到產生新的IP,再由這些新的IP去串接成各種類的數位轉換,這種硬體架構,具備有局部性、模組性、規律性、低成本、高產能等優點,並且由於快速傅立葉轉換本身的優點,在實現某些數位轉換的架構上,可以用較省的硬體去實現,或是可以擁有更佳的產能。
Fast algorithms for N-point shifted discrete Fourier transform (SDFT) are proposed by efficient matrix factorization.The resulted matrix decomposition is realized by a cascade of several basic computation blocks with each block implemented by a parameterized IP module.By combining these modules with different parameters, it is easy to implement a wide variety of digital transforms, such as DCT/IDCT in image/video coding, and modified DCT (MDCT) in audio coding. The transform processors realized using the parameterized IP modules have advantages of locality,modularity,regularity,low-cost,and high-throughput. Furthermore ,the computation accuracy can be easily controlled by selecting different numbers of IP modules with proper parameters in the processors.
CHAPTER 1 INTRODUCTION.................................................................................1
1.1 研究動機........................................................................................................1
1.2 準備工作........................................................................................................2

CHAPTER 2 OVERVIEW..........................................................................................4

CHAPTER 3 演算法與架構......................................................................................7
3.1 SHIFTED DFT .................................................................................................7
3.2 以SHIFTED DFT 計算DCT/IDCT..............................................................8
3.2.1 1D DCT/IDCT的 SDFT實現法..............................................................8
3.2.2用部分N點SDFT實現N點1D DCT/IDCT ................................................9
3.2.3用部分N點SDFT同時實現兩筆N點1D DCT.................................10
3.3以SHIFTED DFT 計算 MDCT ....................................................................12
3.4 SDFT的快速演算法.......................................................................................14
3.4.1 1D DCT/IDCT/MDCT的分解架構........................................................14
3.5基本元件的參數化設計 ...............................................................................16
3.5.1 BUTTERFLY 運算之IP設計................................................................17
3.5.2 CORIDC-BASED之旋轉 .......................................................................18
3.5.3 LIFTING-BASED之旋轉 ......................................................................20
3.6 1D DCT/IDCT/MDCT 之演算法..................................................................22

CHAPTER 4 硬體實作.............................................................................................26
4.1 參數化IP設計之簡介...................................................................................26
4.2 設計流程與驗證...........................................................................................27
4.3 參數化1D N-POINT DCT 和 TEST-PATTERN GENERATOR................29
4.4 參數化1D N-POINT IDCT 和 TEST-PATTERN GENERATOR...............35
4.5 參數化1D N-POINT MDCT 和 TEST-PATTERN GENERATOR.............39
4.6 誤差值的偵測與比較...................................................................................43

CHAPTER 5 分析與比較........................................................................................51

CHAPTER 6 應用....................................................................................................55

CHAPTER 7 總結和未來工作................................................................................60
參考文獻...................................................................................................................61
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