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研究生:何宗哲
研究生(外文):Tsung-Che Ho
論文名稱:針對IEEE802.11a無線區域網路標準設計之正交多頻分工基頻處理器與同步電路
論文名稱(外文):Design of an OFDM Baseband Processor and Synchronization Circuits for IEEE802.11a Wireless LAN Standard
指導教授:張雲南張雲南引用關係
指導教授(外文):Yun-Nan Chang
學位類別:碩士
校院名稱:國立中山大學
系所名稱:資訊工程學系研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2004
畢業學年度:92
語文別:中文
論文頁數:50
中文關鍵詞:無線網路802.11a快速傅立葉轉換傅立葉轉換同步電路基頻處理器
外文關鍵詞:synchronization circuitsFourier transformWLAN802.11abaseband processor
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由於OFDM (Orthogonal Frequency Division Multiplexing)符元(Symbol)有較長的符元長度,可以有效抵抗多路徑通道造成的頻率衰減,OFDM技術已經被廣泛應用於各種先進數位通訊系統,如DVB (Digital Video Broadcast)、WLAN(Wireless Local Area Network)、UWB (Ultra Wide Band)。近幾年來不論是學術或是工業界,如何有效實現OFDM系統已是一大課題。本論文主要探討目前熱門的802.11a OFDM系統之VLSI架構。有效率的OFDM架構設計包括研究其演算法並平衡演算法效能與硬體成本。本論文於系統模擬階段,使用Matlab建構IEEE802.11a基頻傳接機與已知的通道模型,用以改善接收機同步演算法,包括:「封包偵測」、「時間同步」、「載波頻率位移估測」、「通道估測」與「殘餘相位追蹤」。本論文採用在多路徑通道影響與嚴重雜訊下,仍然表現優異之封包偵測與時間同步方法,當SNR>3時,偵測成功率幾近100%。最後,已面積最佳化之適合於VLSI實現之同步模組於本論文中提出,僅需要約5個複數乘法器、388個移位暫存器與一些加法器及簡單的邏輯電路。這些同步模組並與single-path radix-23 FFT/IFFT (Fast Fourier Transform/Inverse FFT)整合為高效率之OFDM基頻處理器暨同步電路。
OFDM (Orthogonal Frequency Division Multiplexing) technology, due to its longer symbol duration that decease the amount of dispersion in time caused by multipath delay spread, has been widely used in many advanced digital communication systems such as DVB (Digital Video Broadcast), WLAN (Wireless Local Area Network), and UWB (Ultra Wide Band). How to realize efficient OFDM systems has been a very important issue for either academic or industry fields in recent years. This thesis aims to explore the VLSI implementation of the OFDM system targeted on its application on the wildly popular IEEE802.11a WLAN systems. An efficient OFDM architecture design involves the algorithm exploration and the tradeoff between the algorithm performance and hardware implementation. Therefore, in this thesis, a Matlab simulation platform for the IEEE802.11a baseband receiver is first built to refine several key synchronization algorithms including frame detection, timing recovery, carrier frequency offset, channel estimation as well as phase tracking under some given channel models. An excellent frame detection and timing recovery method is adopted such that nearly perfect synchronization can be achieved at SNR> 3. Furthermore, area-efficient architecture suitable for VLSI implementation for each synchronization module has also been proposed. In summary, 4 complex multipliers with 388 shift registers are required in our synchronization circuits. These modules are integrated with a core single-path radix-23 IFFT (Inverse Fast Fourier Transform) block to build a highly efficient WLAN baseband.
摘要 i
ABSTRACT ii
誌謝 iii
LIST OF CONTENTS iv
LIST OF TABLES vi
LIST OF FIGURES vii
第一章 簡介 1
1.1 通訊系統簡介 1
1.2 OFDM 系統簡介 1
第二章 IEEE 802.11a傳接機與通道模型 4
2.1 IEEE802.11a基頻傳接機模型 4
2.2 Channel Model 6
2.2.1 Multi-path Channel Model 7
2.2.2 CFO Channel Model 9
第三章 OFDM 基頻處理器電路設計 10
3.1 FFT/IFFT 10
3.1.1 Radix-23 FFT 11
3.1.2 IFFT 15
3.2 Pilots Insertion 16
3.3 Cyclic Prefix Function 16
第四章 接收端同步電路設計 18
4.1 Frame Detection 19
4.1.1 Algorithm 19
4.1.2 Hardware Implementation 21
4.2 Carrier Frequency Offset Synchronization 24
4.2.1 Algorithm 24
4.2.2 Hardware Implementation 26
4.3 Timing Recovery 28
4.3.1 Algorithm 28
4.3.2 Hardware Implementation 31
4.4 Channel Estimation and Compensation 31
4.4.1 Algorithm 32
4.4.2 Hardware Implementation 33
4.5 Phase Tracking 34
4.5.1 Algorithm 34
4.5.2 Hardware Implementation 35
4.6 Overall Synchronization Circuits 35
第五章 結論與未來目標 39
5.1 結論 39
5.2 未來目標 39
第六章 參考文獻 41
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