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研究生:吳松翰
研究生(外文):Sung-han Wu
論文名稱:低功率渦輪碼解碼器之設計與實現
論文名稱(外文):Design and Implementation of Low Power Turbo Code Decoder
指導教授:張雲南張雲南引用關係
指導教授(外文):Yun-nan Chang
學位類別:碩士
校院名稱:國立中山大學
系所名稱:資訊工程學系研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2004
畢業學年度:92
語文別:中文
論文頁數:42
中文關鍵詞:低功率渦輪碼
外文關鍵詞:turbo codelow power
相關次數:
  • 被引用被引用:3
  • 點閱點閱:135
  • 評分評分:
  • 下載下載:30
  • 收藏至我的研究室書目清單書目收藏:0
渦輪碼的低功率設計對現今的通訊系統如第三代通訊系統來說是一個相當重要的研究課題。在渦輪碼的架構中用來儲存分支路徑值以狀態路徑直的記憶體,不論是在功率的消耗或是面積上都占了整個架構的大部分。因此在本論文中是以儲存編碼端的輸入值以及時計算產生分支路徑值而不是儲存計算出的分支路徑值。另外,還提出了一個新的簡化儲存狀態路徑值記憶體的方法,此方法僅需增加少量的額外硬體架構便可減少一半的記憶體數量。此外,相同的設計方法在非遞迴編碼應用上還可以更進一步的簡化軟輸出值計算模組的架構。最後經由實驗結果顯示我們所提出的方法在面積及功率的消耗上分別節省了約40%及13%。
Design of low power Turbo decoder is one of the key issues in many modern communication systems such as 3 GPP. For the Turbo decoder architecture, the memory for the storage of the branch metric and state metric represents a major part of the entire decoder no matter in silicon area or power dissipation. Therefore, instead of saving the computed branch memory, this thesis adopts an alternative approach by saving the input in order to generate the branch memory on line. Furthermore, a novel design of state metric unit is proposed such that the size of the total state metric can be effectively reduced by a half with slightly overhead of adders/subtractors. For non-recursive systematic encoding applications, the same design methodology can further reduce the number of arithmetic units required in the soft-output calculating module. Our preliminary experimental result shows that the proposed design methodology can achieve 40% and 13% reduction on the gate count and power dissipation respectively.
第一章 : 緒論…………………………………………………1
1. 1研究動機……………………………………………………………1
1. 2 各章提要…………………………………………………………2

第二章 : 渦輪碼的原理與架構………………………………3
2.1 渦輪碼的架構………………………………………………………3
2.1.1渦輪編碼器架構………………………………………………………3
2.1.2渦輪解碼器架構………………………………………………………5
2.2 最大事後機率演算法……………………………………………….6
2.3 Log-MAP演算法…………………………………………………….7
2.4 移動式視窗的運作方法…………………………………………….9
第三章 : 渦輪解碼器之硬體設計…………………………..12
3.1 SISO單元………………………………………………………….12
3.1.1 BMC設計………………………………………………………12
3.1.2 ACSOC設計……………………………………………………14.
3.1.3 LLRC設計………………………………………………………17
第四章 : 渦輪解碼器之低功率設計………………………..19
4.1 SISOγ-RAM部分的修正…………………………………………19
4.1.1 Classical solution…………………………………..19
4.1.2 Proposed solution…………………………………….19
4.2 SISOα-RAM部分的修正………………………………………..21
4.2.1 Classical solution……………………………………21
4.2.2 Proposed solution……………………………………21
4.2.3 SMR設計……………………………………………………25
4.3 非遞迴碼的應用………………………………………………….28
4.3.1αRAM修正和非遞迴應用結合的設計……….……………31
第五章 : 結果與討論……………………………………….33
參考文獻……………………………………………………..34
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