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研究生:張嘉玨
研究生(外文):Jia-Jue Chang
論文名稱:IEEE802.11a無線區域網路實體層基頻收發端之系統雛型發展
論文名稱(外文):System Prototyping of the IEEE 802.11a Wireless LAN Physical Layer Baseband Transceiver
指導教授:張雲南張雲南引用關係
指導教授(外文):Yun-Nan Chang
學位類別:碩士
校院名稱:國立中山大學
系所名稱:資訊工程學系研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2004
畢業學年度:92
語文別:中文
論文頁數:46
中文關鍵詞:系統雛型IEEE 802.11a 無線網路基頻收發端實體層數位矽智產
外文關鍵詞:baseband transceiverphysical layerintellectual propertyIEEE 802.11a WLANFPGAprototyping
相關次數:
  • 被引用被引用:3
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  • 下載下載:27
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在室內高速無線通訊網路環境中,IEEE所制訂的802.11系列為市面上一大主流。而本論文根據IEEE所制訂的標準,提出802.11a實體層之電路設計。設計中整合了OFDM處理器、FFT/IFFT模組及維特比解碼器模組,並實作出其餘的主要模組以完成整個實體層基頻電路;本論文以Verilog HDL進行實作,並以C++等高階語言來進行RTL模擬、gate level驗證。本論文採用Altera的DSP Development Board為FPGA平台快速建立一個雛形系統。利用FPGA版上解析度為10位元之AD/DA通道來傳輸時域上的I、Q通道數值,並以此讓傳送端、接收端可互相溝通及傳遞資料。本論文所提出之傳送端電路所使用的邏輯閘數量為81,190,而接收端電路的邏輯閘數量為413,461。
In the high-speed indoor wireless applications, IEEE 802.11 series is the most dominating LAN standard in the current markets. In this thesis, the design issues of the IEEE 802.11a physical layer baseband system are addressed. Various key modules including Viterbi codec, FFT/IFFT module, OFDM synchronous circuit have been integrated with several other modules to constitute the entire baseband system. This system has been implemented by Verilog HDL and verified against with the C-based behavior model. In addition, it will also be prototyped and optimized on the Altera DSP FPGA Development Board. The transmission of the I, Q channel for the time domain singal is emulated by using the 10-bits AD/DA modules on the FPGA board. The experimental results shows that the gate counts of the transmitter and the receiver are 81,190 and 413,461 respectively.
List of Contents
摘要 II
ABSTRACT III
LIST OF CONTENTS IV
LIST OF FIGURES VI
LIST OF TABLES VIII
第一章 導論 1
第二章 整體架構 4
2.1 SIGNAL FIELD 5
2.2 DATA FIELD 6
2.2.1 Service Field 7
2.2.2 Tail Bits 7
2.2.3 Pad Bits 8
第三章 傳送端電路設計 10
3.1 SCRAMBLER 11
3.2 ENCODER 12
3.3 INTERLEAVER 12
3.4 MODULATION 16
3.5 OFDM PROCESSOR FOR TRANSMITTER 16
3.6 WINDOW FUNCTION 17
3.7 CONTROL UNIT 18
第四章 接收端電路設計 20
4.1 OFDM PROCESSOR FOR RECEIVER 20
4.2 DEMODULATION 21
4.3 DEINTERLEAVER 22
4.4 DECODER 23
4.5 DESCRAMBLER 23
4.6 CONTROL UNIT 25
第五章 實作結果與結論 27
5.1 優化電路設計 31
5.2模擬及驗證 32
5.3 FPGA PROTOTYPING 33
5.4 結論 34
第六章 未來工作 35
REFERENCE 36
Reference

[1]IEEE Std 802.11a-1999, “Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) specifications, High-speed Physical Layer in the 5 GHz Band.”

[2]ETSI 1999, “Broadband Radio Access Networks (BRAN) HIPERLAN type 2 Technical Specification; Physical (PHY) Layer.”

[3]J. Heiskala and J. Terry, OFDM Wireless LANs: A Theoretical and Practical Guide, Sams, 2002

[4]T. C. Ho, “Design of an OFDM Baseband Processor and Synchronization Circuits for IEEE 802.11a Wireless LAN Standard,” M.S. Thesis, Department of Computer Science and Engineering, National Sun Yat-Sen University, Kaohsiung, Taiwan, 2004

[5]A. J. Viterbi, “Error Bounds for Convolutional Codes and an Asymptotically Optimum Decoding Algorithm,” IEEE Trans. On Information Theory, IT-13, April 1967.

[6]V. D. Nguyen, and H. P. Kuchenbecker, “Block Interleaving for Soft Decision Viterbi Decoding in OFDM Systems,” Vehicular Technology Conference, 2001. VTC 2001 Fall. IEEE VTS 54th, Volume: 1, Pages:470 - 474 vol.1, 2001
[7]M. C. Ko, “Implementation of Turbo Code Decoder IP Builder,” M.S. Thesis, Department of Computer Science and Engineering, National Sun Yat-Sen University, Kaohsiung, Taiwan, 2004

[8]M. C. Chen, “Design of 802.11a Baseband Transmitter and Synchronization,” M.S. Thesis, Department of Electronics Engineering Institute of Electronics, National Chiao-Tung University, Hsin Chu, Taiwan, 2003

[9]L. N. Lee, “On Optimal Soft-Decision Demodulation,” Information Theory, IEEE Transactions on , Volume: 22 , Issue: 4, Pages: 437 – 444, Jul 1976

[10]S.A. Raghavan and G. Kaplan, “Optimum Soft Decision Demodulation for ISI Channels,” Communications, IEEE Transactions on, Volume: 41, Issue: 1, Pages:83 - 89, Jan. 1993

[11]The Device Architecture of Altera’s APEX EP20KE1500EBC652-1X FPGAs. Available:
http://www.altera.com/products/devices/apex/features/apx-architecture.html

[12]The Overview Device Features of Altera’s APEX EP20K Family. Available: http://www.altera.com/products/devices/apex/overview/apx-overview.html

[13]The Library of Parameterized Modules (LPM) in Quartus II. Available: http://www.altera.com/products/software/pld/products/maxplus2/sfw-lpm.html

[14]The Data Sheet of the Altera DSP Development Board Professional Version. Available: http://www.altera.com/literature/ds/ds_dsp-board-prof.pdf

[15]T. H. Meng, “Design and Implementation of an All-CMOS 802.11a Wireless LAN Chipset,” IEEE Communication Magazine, Aug. 2003
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