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研究生:林文吉
研究生(外文):Wun-Ji Lin
論文名稱:高速相位可調式直接數位式頻率合成器與低功率SRAM設計
論文名稱(外文):A High Speed Phase Adjustable ROM-less DDFS and Low-Power SRAM Design
指導教授:王朝欽
指導教授(外文):Chua-Chin Wang
學位類別:碩士
校院名稱:國立中山大學
系所名稱:電機工程學系研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2004
畢業學年度:92
語文別:中文
論文頁數:61
中文關鍵詞:靜態隨機存取記憶體低功率直接數位式頻率合成器
外文關鍵詞:Low PowerSRAMDDFS
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本論文包含兩個主題,第一個主題是高速相位可調式直接數位式頻率合成器;第二個主題是低功率之靜態隨機存取記憶體設計。
直接數位式頻率合成器使用四倍角公式,不使用任何縮放表(Scaling Table)和錯誤更正表(Error Correction Table),並且加入相位和頻率之可調性,配合通訊系統之實際需求的同時,產生IQ Channel所需之頻率,並加入管線式設計以提昇所輸出之頻率。
低功率之靜態隨機存取記憶體主要使用負字元線 (Word-line)電壓來降低漏電流,來達到低功率效果。因為漏電流會隨著記憶體的容量變大而升高,使得存取產生錯誤,所以使用負字元線來降低漏電流不僅可以達到低功率,而且可以讓讀寫記憶體不會產生存取錯誤。
This thesis includes two topics. The first topic is a high speed phase adjustable ROM-less DDFS (Direct Digital Frequency Synthesizer). The second one is a low-power SRAM design.
The high speed phase adjustable ROM-less DDFS employs trigonometric quadruple angle formula with the adjustability of phase and frequency. Neither any scaling tables nor error correction tables are required. In order to meet demands of general communication systems, the ROM-less DDFS is aimed at generating the frequencies for IQ channels. A pipelining design is adopted in our design to boost the frequency of the DDFS.
The low-power SRAM uses a negative word-line scheme to reduce the leakage current of word-line controlled transistors (WCT). The leakage current increases with the high density of SRAM which might cause reading and writing errors. The negative word-line scheme not only reduces the leakage current as well as the power, but also makes the SRAM operate reliably during read and write cycles.
摘要 i
Abstract ii
第一章 簡介 1
1.1 前言 1
1.2 相關先前DDFS文獻探討 1
1.3 相關先前低功率SRAM文獻探討 2
1.4 論文目的 4
1.5 論文大綱 5
第二章 高速相位可調式直接數位式頻率合成器 6
2.1 頻率合成器簡介 6
2.2 高速相位可調式直接數位式頻率合成器原理介紹 7
2.2.1 三角函數之一階四倍角近似值法 7
2.2.2 誤差函數近似法 9
2.2.3 三角函數之二階四倍角近似法 10
2.3 直接數位式頻率合成器之實作 10
2.3.1 平方器和乘法器 10
2.3.2 直接數位式頻率合成器架構 11
2.3.3 直接數位式頻率合成器之頻率控制 14
2.3.4 直接數位式頻率合成器之相位位移控制 14
2.4 直接數位式頻率合成器之模擬結果 14
2.4.1 閘級模擬結果 14
2.4.2 TimeMill模擬結果 15
2.4.3 晶片實測結果 17
2.4.4 測試結果結論與討論 20
第三章 低功率SRAM設計 21
3.1 SRAM之功率消耗 21
3.2 架構簡介 22
3.3 記憶體單元漏電流分析 23
3.3.1 負字元線電壓 25
3.3.2 負基座電壓 27
3.3.3 效能比較 29
3.4 位元線的預充電和預放電探討 30
3.4.1 6T記憶體單元 31
3.4.2 4T記憶體單元 33
3.5 SRAM的讀寫 34
3.6 其他電路模組 35
3.6.1 感測放大器 35
3.6.2 自我測試電路 36
3.6.3 記憶體時序控制電路 37
3.6.4 記憶體詳細電路 38
3.7 模擬結果 40
3.8 預計操作規格 43
3.8.1 與其他架構比較 38
3.9 測試考量和晶片佈局 44

第四章 總結與相關成果 46
參考文獻 47
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