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研究生:彭子軒
研究生(外文):Peng Tzuhsuan
論文名稱:低抖動高線性電壓控制震盪器
論文名稱(外文):A Low Jitter High Linearity Voltage Controlled Oscillator
指導教授:高家雄
指導教授(外文):Chia-Hsiung Kao
學位類別:碩士
校院名稱:國立中山大學
系所名稱:電機工程學系研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2004
畢業學年度:92
語文別:英文
論文頁數:48
中文關鍵詞:低抖動高線性電壓控制震盪器
外文關鍵詞:High linearityLow jitterVCORegulator
相關次數:
  • 被引用被引用:3
  • 點閱點閱:313
  • 評分評分:
  • 下載下載:54
  • 收藏至我的研究室書目清單書目收藏:0
鎖相迴路電路應用在許多方面。例如時脈訊號的產生與資料回復以及頻率合成器、調頻器、解頻器的應用上。鎖相迴路必須能夠提供緊密跟隨輸入時脈的一個輸出時脈訊號﹔而在高頻環境時,時脈雜訊也隨之增加。雜訊主要的來源在於供應電壓雜訊與基板雜訊。因此在鎖相迴路電路設計中擁有低雜訊抖動是很重要的。在本論文中,我們討論在鎖相迴路系統之中,產生最大雜訊抖動的電壓控制震盪器。

我們提出了一個低抖動的電壓控制震盪器,採用台積電0.35μm 2P4M 混合信號製程完成電路設計。我們在震盪電路中加入穩壓器用來降低供應電壓雜訊,藉此提高整體電路的供應電壓抑制雜訊比。此電路架構提供了一個高度線性的增益(Kvco),可以降低震盪器雜訊並使得鎖相回路擁有更高的穩定度。
Phase locked loops (PLL) are used in many applications. Application examples include clock and data recovery, clock synthesis, frequency synthesis, modulator, and de-modulator. In many circuits, PLL must provide an output clock to follow the input clock closely. For high speed environments, the noises also rise up. Noises mainly come from the power supply and substrate. They produce jitter. A low jitter design is important in PLL circuit. In this thesis, we discuss the Voltage Controlled Oscillator (VCO) which has the largest jitter in PLL system.

We propose a low jitter voltage controlled oscillator designed in TSMC 0.35μm 2P4M Mixed-Signal process technology. We include a regulator to reduce jitter by increasing the VCO PSRR. This structure also provides a high linearity gain (Kvco) which decreases the VCO jitter in the PLL circuit and improve the system stability.
Abstract
Chapte1. Introduction……………………………………………1
Chapter2.Conventional Oscillators
Section 2.1 L-C Tank Oscillator…………………………2
Section 2.2 Relaxation Oscillator………………………………4
Section 2.3 Ring Oscillator.……………………………………5
Section 2.4 Summary of VCOs …………………………………7

Chapter3.The proposed Voltage Controlled Oscillator………8

Section 3.1 Current Controlled Oscillator……………………9
Section 3.1.1 High Speed Schmitt Trigger……………………10
Section 3.1.2 The CCO Circuit………………………………12
Section 3.2 Voltage-to-Current Converter
Section 3.2.1 Type1 V-I Converter…………………………15
Section 3.2.2 Type2 V-I Converter……………………………17
Section 3.3 Regulator……………………………………………19
Section 3.3.1 Self-Biasing Voltage Reference……………20
Section 3.3.2 Cascode Self-Biasing & voltage divider…23
Section 3.3.3 Voltage Follower & Output Driver…………25
Section 3.4 The Proposed Circuits……………………………28



Chapter4.Results & Discussions

Section 4.1 Design Issues…………………………………………30

Section 4.1.1 Jitter Effect……………………………………30
Section 4.1.2 Jitter Definitions………………………………31
.
(a) The Cycle-to-Cycle Jitter…………………………………31
(b) The Period Jitter…………………………………………32
(c) The Long-Term Jitter……………………………………33

Section 4.1.3 VCO Linearity……………………………………34

Section 4.2 The Frequency Versus Voltage Diagrams………36
Section 4.3 Jitter Simulation and Results…………………38
Section 4.4 Layouts and Measured Results…………………41
Section 4.5 Comparison Lists…………………………………45


Chapter5.Conclusion……………………………………………46

Reference…………………………………………………………47
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[2] Djahanshahi, H. and Salama, C.A.T, “Differential CMOS circuits for 622-MHz/933-MHz clock and data recovery applications,” IEEE Journal of Solid-State Circuits, Vol.35, pp.847-855, June 2000.

[3] Behzad Razavi, “Design of Analog CMOS Integrated Circuits,” Ch14. ~ Ch15.
McGraw-Hill Book co. press Preview edition, 2000.

[4] Behzad Razavi, “RF Microelectronics,” Ch8. Prentice Hall Inc press, 1998.

[5] Herzel, F., Winkler, W., and Borngraber, J., “An integrated 10 GHz quadrature LC-VCO in SiGe:C BiCMOS - technology for low-jitter applications,” IEEE Custom Integrated Circuits Conference, pp.293-296, 21-24 Sept. 2003.

[6] Siripruchyanun, M. and Wardkein, P., “Low-voltage high-speed PWM signal generations based on relaxation oscillator,” Asia-Pacific Conference on, Vol.2, pp.371-374, 28-31 Oct. 2002.

[7] Chua-Chin Wang, Yu-Tsun Chien, and Ying-Pei Chen, “A practical load-optimized VCO design for low-jitter 5 V 500 MHz digital phase-locked loop,” IEEE International Symposium on, Vol.2, pp.528-531, 30 May-2 June 1999.

[8] Lizhong Sun and Nelson, D, “A 1.0 V GHz range 0.13 μm CMOS frequency synthesizer,” IEEE Conference on, pp.327-330, 6-9 May 2001.

[9] Sneep, J.G. and Verhoeven, C.J.M., “A new low-noise 100-MHz balanced relaxation oscillator,” IEEE Journal of Solid State Circuits, Vol.25, pp.692-698, Jun 1990.

[10] TOUMAZOU , C., LIDGEY , F.J., and HAIGH, D.G, “Analogue IC Design-the Current-Mode Approach,” 1990.

[11] R. Jacob Baker, Harry W. Li and David E. Boyce, “CMOS Circuit Design, Layout, and Simulation,” IEEE PRESS, 1998

[12] Yang, H.C., Lee, L.K., and Co, R.S, “A low jitter 0.3-165 MHz CMOS PLL frequency synthesizer for 3 V/5 V operation,” IEEE Journal of Solid State Circuits, Vol.32, pp.582–586, April 1997.

[13] Herzel, F and Razavi, B, “A study of oscillator jitter due to supply and substrate noise,” IEEE Transactions on, Vol.46, pp.56 – 62, Jan. 1999.

[14] Lin Yijing and Sheng Shimin, ”A novel low jitter pll clock generator with supply noise insensitive design,” ASIC, Proceedings. 4th International Conference on, pp.259–261, 23-25 Oct. 2001.

[15] Eckhardt, J.P. and Jenkins, K.A, “PLL phase error and power supply noise [microprocessors],” IEEE 7th topical Meeting on, pp.73–76, 26-28 Oct. 1998.

[16] E. Vittoz and J. Fellrath, “CMOS Analog Integrated Circuits Based on Weak Inversion Operation,” IEEE Journal of Solid State Circuits, Vol. SC-12, No. 3, pp.224-231, June 1977.

[17] Hsiang-Hui Chang, Shang-Ping Chen, and Shen-Juan Liu, “A shifted-averaging vco with precise multiphase outputs and low jitter operation,” European Solid-State Circuits, pp.16-18 Sept. 2003.

[18] Chang-Hyeon Lee, Jack Cornish, Kelly McClellan, and John Choma, Jr. “Design of low jitter PLL for clock generator with supply noise insensitive VCO,” IEE Vol.37, 24 May 2001.

[19] Jae-shin LEE, Woo-kang JIN, Gun-sang LEE and Suki KIM, “Wide Range PLL for EFM Data Recovery of 64X Speed CD-ROMs,” Journal of the Korean Physical Society, Vol. 38, pp.167-172, March 2001.

[20] Kuo-Hsing Chen, Huan-Sen Liao, and Lin-Jiunn Tzou, “A low jitter and low power phase-locked loop design,” IEEE International Symposium on Circuits and Systems, May 28-31, 2000.
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