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研究生:陳俊智
研究生(外文):Chun-Chih Chen
論文名稱:NTSC數位影像解碼器與多重符號編碼解碼器
論文名稱(外文):NTSC Digital Video Decoder and Multi-Symbol Codec
指導教授:王朝欽
指導教授(外文):chua-chin wang
學位類別:碩士
校院名稱:國立中山大學
系所名稱:電機工程學系研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2004
畢業學年度:92
語文別:中文
論文頁數:70
中文關鍵詞:固定長度編碼可變長度編碼影像解碼器
外文關鍵詞:Fixed-length CodingVideo DecoderVariable-length Coding
相關次數:
  • 被引用被引用:5
  • 點閱點閱:339
  • 評分評分:
  • 下載下載:0
  • 收藏至我的研究室書目清單書目收藏:0
在本論文的第一部份我們提出了一個數位化的NTSC影像解碼器。在這一個全數位的設計中包含了一個直接數位頻率合成器和一個用來追蹤鎖定解調變時的載波的數位鎖相迴路。因此,整個數位化影像解碼器的複雜度可以大幅降低。此設計的面積為6.0平方公厘,三萬九千個邏輯閘。當本設計運作在21.48MHz時的功率耗損為86mW。

第二個題目中我們提出了一個在可變長度編碼和固定長度編碼之間轉換的一個編碼解碼器。在此設定中可以避免可變長度編碼的缺點,並保留它的優點。我們提出的編碼解碼器會將可變長度編碼轉換成固定長度的封包,如此一來在硬體上解碼時就可以平行的進行。此設計會將其他符號嵌入至固定長度封包內的多餘位元,因而其衍生之編碼解碼器可以緩和固定長度編碼原有的低壓縮率的問題。
The first topic of this thesis proposes a digital video decoder for NTSC. The new fully digital design employs a DDFS (digital direct frequency synthesizer) and an adaptive digital PLL to track and lock the demodulation carrier. The complexity of the digital video decoder, hence, is drastically reduced. The overall cost of the proposed design is 6.0 mm2 (39K gates). The maximum power dissipation is 86 mW at the hightest clock rate which is 21.48 MHz.

The second topic is to carry out a codec (encoder-decoder) design for interfacing variable-length and fixed-length data compression. The poor memory efficiency caused by the variable-length words converting into a fixed-length packet such that the compression can be hardwaredly and parallelly processing is significantly improved. The proposed codec is to encode more symbols in the redundant bits of the padding bits of the fixed-length packets. This novel encoding scheme relaxes the intrinsic poor bit rate of the traditional fixed-length data compression.
摘要 i
Abstract ii
第一章 簡介 1
1.1 前言 1
1.2 文獻探討 3
1.3 論文目的 4
1.4 論文大綱 5
第二章 NTSC數位影像解碼器 6
2.1 簡介 6
2.2 電路架構 11
2.2.1 亮度彩度分離器-Y/C Separator 12
2.2.2 鎖相迴路-Phase Locked Loop 15
2.2.3 彩度解調器-Chroma Demodulator 19
2.3 模擬結果 21
2.3.1 MATLAB 系統模擬 21
2.3.2 RTL模擬 23
2.3.3 閘級模擬 25
2.3.4 佈局後驗證模擬 26
2.3.5 晶片佈局 27
2.3.6 操作規格 29
2.4 量測結果與結論 29
第三章 多重符號編碼解碼器 33
3.1 簡介 33
3.2 多重符號編碼解碼器之演算法 35
3.2.1 2-1多重符號編碼演算法 36
3.2.2 2-1多重符號解碼演算法 38
3.3 演算法實作(I)-僅適用於傾斜樹  40
3.3.1 壓縮效能分析 41
3.3.2 3-2多重符號編碼器實作 42
3.3.3 3-2多重符號解碼器實作 43
3.3.4 模擬結果 46
3.3.5 晶片佈局 50
3.3.6 操作規格 52
3.3.7 量測結果與討論 52
3.4 演算法實作(II)-適用於所有的赫夫曼樹  55
3.4.1 壓縮效能分析 56
3.4.2 2-1多重符號編碼器實作 58
3.4.3 2-1多重符號解碼器實作 59
3.4.4 模擬結果 61
3.4.5 晶片佈局 63
3.4.6 預計操作規格 63
第四章 結論與相關成果 67
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