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研究生:鄭欽仁
研究生(外文):Chin-ren Cheng
論文名稱:第三代行動通訊系統低功率渦輪解碼器實現
論文名稱(外文):An Implementation of Low-Power Turbo Decoder for 3GPP
指導教授:李志鵬李志鵬引用關係
指導教授(外文):Chih-Peng Li
學位類別:碩士
校院名稱:國立中山大學
系所名稱:通訊工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2004
畢業學年度:92
語文別:中文
論文頁數:84
中文關鍵詞:渦輪碼
外文關鍵詞:Turbo code
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由於渦輪碼的架構簡單,並且能夠提供相當優越的錯誤更正能力,因此近年來廣泛地被應用在各種無線通訊系統,包括第三代無線通訊系統。但由於無線通訊系統攜帶電池的關係,因此使得低功率消耗一直成為渦輪碼設計的重點之ㄧ。但由於渦輪碼在實現上,需消耗大量的記憶體,並且運算過程複雜,因此容易造成大量的功率消耗,所以如何能有效地降低功率消耗,成為近幾年渦輪解碼器設計的重點。
在本論文中,我們針對3GPP的渦輪碼規格,來實現低功率消耗的渦輪解碼器:透過在解碼器的後端部分,加入CRC機制當作決定是否停止重覆解碼運算的條件,以減少不必要的重覆解碼運算,達到降低渦輪解碼器功率消耗的目的。並透過MATLAB軟體模擬和FPGA來做硬體驗證。
Because of the simple architecture and excellent error correcting capability, Turbo code has been adopted in many wireless communication standards, including the third generation wireless communication systems, 3GPP and 3GPP2. However, low power turbo decoder design would become the most important issue in mobile communication systems because of the limited battery life.
In the thesis, we use the cyclic redundancy check (CRC) as the stopping criterion in the implementation of turbo decoder design to reduce the unnecessary power consumption. We use the MATLAB simulation and FPGA simulation to verify our design.
第一章 緒論…………………………………………………………………………1
1.1 研究動機…………………………………………………………………..1
1.2 研究方法與內容…………………………………………………………..2
1.3 論文章節提要……………………………………………………………..2
第二章 渦輪碼的基本原理…………………………………………………………3
2.1 渦輪碼的編碼架構………………………………………………………..3
2.1.1 遞迴系統迴旋編碼器(RSC Encoder) ..............................................4
2.1.2 交錯器(Interleaver)………………………………………………....5
2.2 渦輪碼的解碼架構………………………………………………………..8
2.2.1 對數相似比值的概念………………………………………………8
2.2.2 軟式輸出入解碼器(SISO decoders)和反覆解碼(Iterative decoding)
……………………………………………………………………..10
2.2.3 渦輪碼的解碼架構………………………………………………..12
2.3 MAP、Max-Log-MAP和Log-MAP演算法……………………………14
2.3.1 MAP演算法(MAP Algorithm)……………………………………15
2.3.2 Max-Log-MAP演算法……………………………………………23
2.3.3 Log-MAP演算法………………………………………………….25
2.4 渦輪碼在3GPP的應用………………………………………………….28
2.4.1 3GPP渦輪碼編碼器………………………………………………29
2.4.2 3GPP渦輪碼內部交錯器…………………………………………31
2.5 渦輪碼的效能分析………………………………………………………37
第三章 實現渦輪解碼器的相關主題……………………………………………..39
3.1 可移動視窗方法(Sliding Window Method)實現MAP解碼器…………39
3.2 MAP解碼器的硬體設計考量…………………………………………...43
3.2.1 使用定點方式表示數值(fixed-point arithmetic)和精確度
(precision)的分析……………………………………………….44
3.2.2 查表大小(LUT size)與量化(Quantization)………………….......46
3.2.3 前向運算處理器和後向運算處理器的個數……………………47
3.2.4 可移動視窗方塊的大小(Sliding Window size)…………………47
3.2.5 MAP解碼器所對應的記憶體架構……………………………..48
3.3 低功率渦輪解碼器的設計方法………………………………………….50
3.3.1 降低解碼器的運算複雜度………………………………………50
3.3.2 使用定點方式和有限精確度實現渦輪解碼器…………………51
3.3.3 使用可移動視窗方法實現MAP解碼器的設計………………..51
3.3.4 減少路徑運算……………………………………………………51
3.3.5 設定停止條件(Stopping Criterion)來減少渦輪解碼器的重
覆運算次數……………………………………………………..52
3.3.5.1 從解碼資料的解碼位元(decoded bits)設定停止條件……52
3.3.5.2 從解碼資料的可靠度(reliability)設定停止條件………….53
3.3.5.3 適應性重覆解碼(adaptive iteration)法則…………………54
第四章 3GPP低功率渦輪解碼器的實現………………………………………...58
4.1 3GPP渦輪解碼器的架構……………………………………………….58
4.1.1 3GPP渦輪解碼器中的MAP解碼器架構……………………….59
4.1.2 3GPP渦輪碼交錯器和解交錯器的硬體架構…………………...70
4.1.3 3GPP渦輪解碼器的硬體架構…………………………………...73
4.2 MATLAB模擬…………………………………………………………...77
4.3 FPGA模擬驗證………………………………………………………….79
第五章 結論………………………………………………………………………..80
5.1 結論………………………………………………………………………80
5.2 未來展望…………………………………………………………………80
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