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研究生:王鴻凱
研究生(外文):Hong-Kai Wang
論文名稱:矽奈米線選擇性成長和控制
論文名稱(外文):Selective growth and control of Si nanowires
指導教授:黃惠良黃惠良引用關係蕭錫鍊蕭錫鍊引用關係
指導教授(外文):Huey-Liang HwangHsi-Lien Hsiao
學位類別:碩士
校院名稱:國立清華大學
系所名稱:電子工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2003
畢業學年度:92
語文別:中文
論文頁數:72
中文關鍵詞:矽奈米線電場方向
外文關鍵詞:Si nanowireelectric fielddirectionorientation
相關次數:
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  • 收藏至我的研究室書目清單書目收藏:1
本論文研究目的在發展矽奈米線合成之技術及利用電場輔助控制矽奈米線成長方向,並提出一套藉由電場輔助成長定向機制的合理解釋。
我們沉積一層金奈米薄膜並製造簡單圖形,成功的藉由低壓化學氣相沉積方法在460℃以上去合成無規則方向性的矽奈米線。此外,我們製造出由鉻和金所組成特殊電極,利用加高電場達到從陰極適當的地方成長出矽奈米線且藉由強電場去控制矽奈米線成長方向。我們也成功在玻璃基板上利用高電場去控制矽奈米線成長方向,並藉由掃描電子顯微鏡(SEM)圖,我們觀察到矽奈米線直接從陰極端長出並且朝向陽極端成長,最後停止在陽極端上,這條矽奈米線直徑大約有45奈米寬,長度大約3微米長。因此,我們藉由觀察和分析SEM圖,提出在電場輔助下,由於場發射效應造成陰極局部溫度上升並使金暴露在矽烷下,藉由氣-液-固相成長機制長出矽奈米線,在成長過程中,由於陰電性不同,造成電荷轉移和電力作用下,促使矽奈米線沿著電場方向朝向陽極端成長。
由於成長溫度在460℃,在玻璃熔點下,利用這個方法去製造出將陰極當成源極端,陽極當成汲極端和矽奈米線當成通道,然後要做出薄膜電晶體或其他奈米元件就比其他目前成長後再定向的方法更加快速,並且有機會取代目前利用雷射將非晶矽轉變成多晶矽的方法,因此此方法非常具有經濟效益。此外,這個方法可能也可廣泛的應用在其他半導體奈米線上,例如磷化銦,氮化鎵,砷化銦等等。

In our study, we have developed the technology of Si nanowire synthesis and used electric field to control the orientation of Si nanowires. We have also put forward a reasonable explanation for the growth mechanism.
We fabricated the pattern from depositing a nanoscale gold metal film then successfully synthesized silicon nanowires with random orientation above 460℃ by chemical vapor deposition (CVD). In addition, special metal electrode consisting of chromium then gold metal was fabricated and by utilizing a strong electric field, Si nanowire was grown at suitable position from the cathode. We successfully utilized a strong electric field to control the orientation of Si nanowires on the glass substrate. We observed the Si nanowire of 45nm diameter and 3 m length grown from the cathode, initially extend into the air towards the anode along the direction of the local electric field. Finally the Si nanowire stopped on the anode. Therefore, we observed and analyzed Si nanowires by SEM, then put forward the electric field assisted growth mechanism. The Au film exposed to air due to the effect of field emission caused an increase in the local temperature of the cathode. By electric force and transference of charge due to the difference of electronegativity of Si and Au, Si naowires were grown according to vapor-liquid-solid ( VLS ) mechanism along the direction of electric field towards the anode during synthesis.
The temperature of the growth is 460℃, below the melting point of the glass, so we utilized our results to use cathode as the source, anode as the drain and Si nanowire as the channel. Then this technology with added economic benefits can be used to fabricate thin film transistor ( TFT ) or other nanodevices. Also it can be used to substitute for excimer laser annealing (ELA), a method which transform amorphous silicon into poly silicon and may be widely applied to other semiconductor nanowires, such as InP, GaN, InAs.

Contents
Chinese Abstract ............................................................................................... i
English Abstract ................................................................................................ ii
誌謝辭 …...….……........................................................................................... iv
Contents ............................................................................................................ v
List of Figures ..................................................................................................... vii
List of Tables …………………………………………………………………… xii
Chap.1 Introduction
1-1 Introduction to nanotechnology…………………………………… 1
1-2 One dimensional (1-D) nanomaterials ……………………………. 1
1-3 Synthesis of one dimensional (1-D) nanomaterials……………….. 3
1-3-1 Synthesis of carbon nanotubes ……………………………… 4
1-3-1-1 Arc-discharge method .……………………………… 4
1-3-1-2 Laser vaporization ………………………………… 5
1-3-1-3 Chemical vapor deposition (CVD) ………………. 6
1-3-2 Synthesis of nanowires…………………………………….. 7
1-3-2-1 Laser vaporization ………………………………. 7
1-3-2-2 Chemical vapor deposition ………………………. 8
1-3-2-3 Lithography and etching …………………………. 9
1-4 Growth mechanism of nanowires ……………………………….. 9
1-5 Applications of one dimensional nanomaterials …………………. 11
1-6 Positioning and orientation control of one dimensional (1-D) nanomaterials………………………………………………………. 12
1-7 Motivation ………………………………………………………. 13
References …………………………………………………………… 27
Chap.2 Experimental method and characterization
2-1 Fabrication of metal electrode ………………………………......... 31
2-2 Growth of Si nanowires ………………………………………… 32
2-3 Characterization ………………………………………………….. 33
2-4 Equipments used in our experiment ……………………………… 33
2-4-1 DC sputter system ………………………………………… 34
2-4-2 LPCVD system ……………………………………………. 35
References……………………………………………………………. 46
Chap.3 Results and Discussion
3-1 Synthesis of Si nanowires and SEM images………………………. 47
3-2 Synthesis of Si nanowires assisted by electric field and SEM……….. 48
3-3 Effect of thickness and material of the electrodes…………………. 50
3-4 Growth mechanism of Si nanowires assisted by electric field ………..52
References …………………………………………………………… 69
Chap.4 Conclusion
Chap.5 Future work
List of Figures
Fig. 1-1. Various forms of carbon: diamond, graphite, nanotube, and fullerene
Fig. 1-2. HRTEM image of nanotubes
Fig. 1-3.Classification of SWCNT: (a) armchair tubule, (b) zigzag tubule, (c) chiral tubule
Fig. 1-4. (a) Geometry and alignment of 4nm graphite rods showing the appearance of the rods after the arcing experiment (b) Photograph of the anode(left) and graphite rods showing the appearance of the rods after the arcing experiment
Fig. 1-5. Oven laser-vaporization apparatus
Fig. 1-6. (a) Schematic of fabrication process, (b) SEM image of the resulting hexagonally ordered array of carbon nanotubes fabricated using the method in (a)
Fig. 1-7. (a) Oven laser-vaporization apparatus, (b) Si nanowires consist of a very uniform diameter crystalline core surrounded by amorphous SiOX coating and HRTEM image
Fig. 1-8. (a)SEM image of Si NWs grown from the 10 nanoclusters and scale bar is
20nm, (b) HRTEM image of 10.7nm-diam Si NWs, (c) HRTEM image of
20.6 nm-diam NWs
Fig. 1-9. (a) Si nanowires began to emerge from the nanopores, (b) Gold balls present at the tips of the Si nanowires, (c) TEM image of nanowire
Fig 1-10. Schematic illustration of vapor-liquid-solid nanowire growth mechanism ncluding four stages: (a) alloying, (b) supersaturation, (c) nucleation and (d) axial growth.
Fig.1-11. The phase diagram of silicon-gold alloy
Fig.1-12. In situ TEM images recorded during the process of nanowire growth. (a) Au nanoclusters in solid state at 500℃, (b) Alloying is initiated at 800℃, at this stage Au exists mostly in solid state, (c) Liquid Au/Ge alloy, (d) The nucleation of a Ge nanocrystal on the alloy surface, (e)Ge nanocrystal elongates with further Ge condensation, and (f) eventually forms a wire (g) The phase diagram of Ge-Au allay.
Fig. 1-13. Emitting image of fully sealed SWNT-FED at a color mode with red, green, and blue color phosphor by Samsung-Electronics
Fig. 1-14. A single MWNT probe microscopy tip
Fig. 1-15. Single- and multi-wall carbon nanotube field-effect transistors
Fig.1-16. silicon nanowire transistor
Fig. 1-17. (a) Si NW nanosensor for pH detection (b) real-time detection of protein binding
Fig. 1-18. (a) Crossed SiNW junctions. (b) n+-p-n SiNW bipolar transistors. (c) SiNWcomplementary inverters
Fig1-19. Flow chart of AFM manipulation
Fig1-20. Schematic of fluidic channel structure
Fig1-21. Parallel and orthogonal assembly of nanowires with electric field
Fig1-22. (a) (b) Structure of sample (c) aligned nanotubes after electric field directed growth
Fig. 2-1. Flow diagram for the synthesis and characterization of Si nanowires
Fig 2-2. (a) Design diagram of mask pattern, (b) SEM image of electrodes for Cr/Au/Cr sample, (c) OM image of electrodes for Cr/Au/Cr sample, (d) The cross-section of (b) and (c), (e) SEM image of electrodes for TEOS /Cr/Au/Cr sample, (f) OM image of electrodes for TEOS /Cr/Au/Cr sample, (g) he cross-section of (e)and (f).
Fig. 2-3. The flow chart of fabricated electrodes
Fig. 2-4. (a) Real diagram of sample holder, (b) sketch map of sample holder
Fig. 2-5. Growth diagram of silicon nanowires
Fig. 2-6. A ray of electron impinging on a sample producing electrons, X-ray and
Photons
Fig. 2-7. Schematic description of the operation of an SEM
Fig. 2-8. Schematic of Hitachi Model S-4000 FMSEM
Fig. 2-9. (a) DC sputter system, (b) schematic diagram of DC-power sputter deposition
Fig. 2-10. Important processes in sputter deposition
Fig. 2-11. (a) LPCVD system, (b) schematic diagram of LPCVD equipment
Fig. 3-1. Low-magnification images of silicon nanowires in sample 1 at (a) 400℃ (b) 450℃ (c) 460℃ (d) 470℃ (e) 500℃ (f) A magnified view of (e)
Fig.3-2. Low-magnification images of silicon nanowires in sample 8 at (a) 460℃ (b) 470℃ (c) 500℃. (d), (e)and (f) A magnified view of (a) , (b)and (c) respectively
Fig.3-3. (a)High-magnification SEM images of silicon nanowires at 500℃ in sample 1 (b) and (c) EDS analysis for different position of Si nanowire
Fig.3-4. (a)High-magnification SEM images of silicon nanowires at 500℃ in sample 8 (b) and (c) EDS analysis for different position of Si nanowire
Fig.3-5. SEM images of silicon nanowires in sample 2 at (a) 470℃ (b) 490℃ (c) 500℃.
Fig.3-6. SEM images of silicon nanowires grown in various electric field in sample at 460℃. The spacing between the tip of the two electrodes is 6 m (a) 0V (b) 100 V
Fig.3-7. Low-magnification images of silicon nanowires in sample 2 at 460℃ with 100V (a), (b), (c) and (e) at different pads, (d) high-magnification image of the square in the (c)
Fig.3-8. (a)Low-magnification images of silicon nanowires in sample 2 at 460℃ with 100V (b) and (c) high-magnification image of the square in the (a).
Fig.3-9. (a) and (b) Low-magnification images of the sample 2 without the growth of silicon nanowires at 460℃ with 100V (c) and (d) high-magnification image of the arrow 1 and 2 in the (b).
Fig.3-10. (a) Low-magnification image of the sample 2 at 460℃ with 100V(b) High-magnification image of (a).
Fig.3-11. (a) Low-magnification image of the sample 1 annealed at 470℃ (b) High-magnification image of (a)
Fig.3-12. (a) SEM image of the sample 2 annealed at 470℃ (b) SEM image of the sample 2 annealed with about 15V/ m at 470℃
Fig.3-13. (a) SEM image of the sample 3 without any treatment (b) SEM images of the sample 3 annealed at 470℃
Fig.3-14. (a) SEM image of the sample 4 annealed at 470℃ (b) SEM image of the sample 4 annealed with about 15V/ m at 470℃
Fig.3-15. (a) SEM image of the sample 5 annealed at 470℃ (b) SEM image of the sample 5 annealed with about 15V/ m at 470℃
Fig.3-16. (a) SEM image of the sample 6 annealed at 470℃ (b) SEM image of the sample 6 annealed with about 15V/ m at 470℃
Fig.3-17. (a) SEM image of the sample 7 annealed at 470℃ (b) SEM image of the sample 7 annealed with about15V/ m at 470℃ (c) and (d) High-magnification image of (a) and (b).
Fig.3-18. (a) Low-magnification image of silicon nanowires in sample 7 at 460℃ with 20V (b), (c) and (d)the images obtained with different electric pads
Fig.3-19. (a) Low-magnification image of silicon nanowires in sample 7 at 460℃ with 20V (b)and (c) High-magnification images of (a)
Fig.3-20. (a) Low-magnification images of silicon nanowires in sample 7 at 460℃ with 20V (b), (c) and (d) High-magnification images of (a)
Fig.3-21. Diagram of rough sketch of the electric field
Fig.3-22. Flow chart of the growth mechanism of Si nanowires assisted by electric field
Fig.5-1. The schematic diagram of TFT fabricated by Si Nanowire
Fig.5-2. The schematic diagram of the MOS device fabricated by crossing two Si Nanowires.
List of Tables
Table 2-1 Operating parameters for the thickness of make films for different shapes
Table 2-2 Operating parameters of DC sputter for the deposition of metal films
Table 2-3 Operating parameters of TEOS oxide deposition by PECVD
Table 3-1. The parameters for experiment 1.

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