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研究生:張智淳
研究生(外文):Chih-Chun Chang
論文名稱:符合晶片匯流排規格之正反向離散小波轉換的可參數化矽智財產生器
論文名稱(外文):A Parameterized On-Chip-Bus-Compliant FDWT/IDWT Accelerator IP Generator
指導教授:林永隆林永隆引用關係
指導教授(外文):Youn-Long Lin
學位類別:碩士
校院名稱:國立清華大學
系所名稱:資訊工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2004
畢業學年度:92
語文別:英文
論文頁數:48
中文關鍵詞:JPEG2000離散小波轉換矽智財單晶片系統晶片
外文關鍵詞:JPEG2000DWTSIPSOC
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  • 被引用被引用:0
  • 點閱點閱:95
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  • 下載下載:10
  • 收藏至我的研究室書目清單書目收藏:0
中文摘要

我們在這篇論文中提出一個不同參數係數的離散小波轉換硬體加速器產生器。除了在JPEG2000規格中使用的(5,3)和(9,7)濾波器,其他的濾波器像是(9,3),(6,10)和(2,2)也都可產生。這樣將來有不同應用需要使用到離散小波轉換,都可以以此產生器來快速產生。

所產生的離散小波轉換矽智財可做正向及反向的離散小波轉換。並且我們對於其效能以及耗電功率做最佳化。以此架構作為其他不同濾波器架構的基礎。接著我們分析lifting-based離散小波轉換的特性,針對各種不同係數的濾波器做分解,並且設計其相對應的架構。

我們也提供符合晶片匯流排規格(AMBA)的介面和對應的驅動程式來做系統晶片(SOC)整合。對於矽智財的介面,可能會因為不同的系統,而有不同的需求。因此我們提供了兩種介面,以中央控制器(CPU)傳送資料,另一種則是使用直接記憶體讀取(DMA)和中斷機制(interrupt)配合使用,以期達到最佳效果。

另外我們在系統晶片平台上實際整合我們的矽智財到JPEG2000應用程式。實驗結果展示了我們的矽智財產生器的確能有效得改進矽智財設計的效率。
We propose a generator for hardware acceleration of Discrete Wavelet Transform (DWT) with various coefficient parameters. Not only (5, 3) and (9, 7) DWT filters defined in the JPEG2000 image compression standard but also other filters, such as (9, 3), (6, 10) and (2, 2), can also be generated. The generated DWT IP can perform both forward and inverse transform (FDWT and IDWT). Our generator also provide on-chip-bus interface compliant with AMBA protocol and associated device driver so that the generated IPs are ready for SOC integration. We verify the proposed approach by integrating generated IPs into an SOC platform running JPEG2000 application software. Experimental results demonstrated that the proposed approach is indeed effective in enhancing the productivity of hardware accelerator IP design.
Contents
ABSTRACT I
CONTENTS II
LIST OF FIGURES IV
LIST OF TABLES V
CHAPTER 1 6
INTRODUCTION 6
CHAPTER 2 9
PREVIOUS WORK 9
CHAPTER 3 12
PROPOSED DWT ARCHITECTURE 12
3.1 DWT TOP ARCHITECTURE 12
3.1.1 COMBINE FORWARD DWT AND INVERSE DWT 12
3.1.2 THE BIT PRECISION 14
3.2 LOW-POWER AND HIGH-PERFORMANCE DESIGN 15
3.2.1 IMPROVED SYMMETRIC EXTENSION MODULE 15
3.2.2 CANONIC SIGNED DIGIT (CSD) MULTIPLIERS 18
3.2.3 USING RETIMING TO IMPROVE PERFORMANCE 20
CHAPTER 4 21
GENERALIZED DWT 21
4.1 LIFTING-BASED DWT THEORY 22
4.2 THE FACTORIZATION OF DIFFERENT WAVELET FILTERS 23
4.2.1 The factorization of odd taps wavelet filters 23
4.2.2 The factorization of even taps wavelet filters 25
4.2.3 The factorization of inverse discrete wavelet transform 26
4.3 GENERALIZED DWT ARCHITECTURE 27
4.3.1 Top local DWT architecture 27
4.3.2 Predict/Update module 28
4.3.3 Signal extension module 30
4.3.4 Control unit module 31
CHAPTER 5 32
DWT IP IMPLEMENTATION 32
5.1 SYNTHESIS RESULT 33
5.2 DESIGN-FOR-TEST SYNTHESIS REPORT AND ATPG RESULT 33
5.3 IP QUALIFICATION 34
5.4 DESIGN MODELS 34
5.4.1 Programmable parameter 35
5.4.2 Reconfigurable parameter 36
CHAPTER 6 37
VERIFICATION AND INTEGERATION 37
6.1 TESTBENCH 37
6.2 BUS INTERFACE 38
6.3 ADVANCE BUS INTERFACE 39
6.4 DEVICE DRIVER 40
6.5 A HW/SW CO-DESIGN JPEG2000 40
6.6 EXPERIMENT REPORT 41
CONCLUSIONS 44
Bibliography

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