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研究生:詹凱元
研究生(外文):Kai-Yuan Jan
論文名稱:系統單晶片設計方法與其在影像壓縮系統的應用研究
論文名稱(外文):A Platform-Based SOC Design Methodology and its Application on JPEG Decoding
指導教授:林永隆林永隆引用關係
指導教授(外文):Youn-Long Lin
學位類別:碩士
校院名稱:國立清華大學
系所名稱:資訊工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2004
畢業學年度:92
語文別:英文
論文頁數:32
中文關鍵詞:系統單晶片矽智財影像壓縮內嵌式硬體加速器高階合成系統整合軟硬體共同設計
外文關鍵詞:SOCSIPAMBAARMEmbeddedHigh Level SynthesisSOPCAHB
相關次數:
  • 被引用被引用:0
  • 點閱點閱:138
  • 評分評分:
  • 下載下載:15
  • 收藏至我的研究室書目清單書目收藏:0
我們提出一個平台式 (Platform-Based) 系統單晶片 (System-on-Chip) 的設計方法。在一般的系統單晶片發展電路驗證板中包含一個內嵌式的RISC CPU及可程式化的FPGA,使用者可在此環境中實現特定的應用系統,其軟體及硬體各別會在CPU及FPGA上執行。在此設計方法中包含了一個完整設計流程及不同的輔助設計工具,可用來各別作軟體/硬體設計時的分割、自動產生AHB相容的硬體加速器、內嵌式軟體的設計及編譯、整合系統中的軟體/硬體並作共同模擬、整個系統在電路驗證板上的驗證。我們也以JPEG Decoder為例,說明如何以提出來的方法在此平台上以軟體/硬體共同設計的方法來實現此影像解壓縮的系統單晶片。一開始我們會先找出JPEG Decoder中的計算瓶頸,並把此計算瓶頸的部分以AMBA相容的硬體加速器來實現,其它部分則以軟體實現並在RISC CPU上執行。由實驗結果可看到藉由我們提出的設計方法可以很快地用來發展矽智財 (Silicon Intellectual Properties) 並作系統整合的驗證,最後可完成整個系統的原型 (Prototyping)
We describe a platform-based design methodology for system-on-a-chip (SOC). A commercially available chip consisting of an embedded 32-bit RISC CPU core and a field programmable gate array (FPGA) module is used to implement applications that require both a program running on the CPU and hardware acceleration performed by the FPGA. The methodology consists of flow and tools for hardware/software partitioning, automatically synthesizing hardware accelerator, interface generation, software design/compilation, integrated hardware/software co-simulation, and whole system verification. We also present a case study of implementing an image decoder in a hardware/software co-design fashion on the platform using the described methodology. Computational intensive part of the application is methodologically identified and implemented as an AMBA compliant silicon intellectual property and successfully integrated with the software program running on the RISC CPU core. Experimental results show that the platform-based methodology is indeed effective for IP development/verification and fast prototyping.
ABSTRACT--------------------------------------------- II
CONTENTS-------------------------------------------- III
LIST OF FIGURES--------------------------------------- V
LIST OF TABLES--------------------------------------- VI
CHAPTER 1 INTRODUCTION--------------------------------1
CHAPTER 2 PREVIOUS WORK------------------------------ 4
2.1 HARDWARE/SOFTWARE CO-DESIGN---------------------- 4
2.2 PLATFORM-BASED SOC DESIGN------------------------ 5
2.3 IP INTEGRATION----------------------------------- 6
CHAPTER 3 SOC DESIGN FLOW---------------------------- 7
3.1 PLATFORM AND METHODOLOGY------------------------- 7
3.2 SOPC BUILDER------------------------------------- 9
CHAPTER 4 JPEG DECODER IMPLEMENTATION---- ---------- 11
4.1 PERFORMANCE REQUIREMENT------------------------- 11
4.2 PROFILING--------------------------------------- 12
4.3 HW/SW PARTITIONING------------------------------ 13
4.4 AUTOMATIC SYNTHESIS OF AHB
COMPLIANT IDCT HARDWARE ACCELERATOR--- --------- 15
4.4.1 High Level Synthesis Flow-------------------- 16
4.4.2 AHB Interface-------------------------------- 17
4.5 EMBEDDED SOFTWARE------------------------------- 18
4.5.1 Memory Management Unit (MMU)----------------- 20
4.5.2 Way Over Simple File System (WOSFS)---------- 21
4.6 HW/SW CO-SIMULATION----------------------------- 22
CHAPTER 5 FPGA PROTOTYPING AND PERFORMANCE ANALYSIS- 24
CHAPTER 6 CONCLUSIONS------------------------------- 27
BIBLIOGRAPHY----------------------------------------- 29
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