臺灣博碩士論文加值系統

系統單晶片設計(System-on-Chip)有賴於在系統平台上整合可重複使用且已經完成設計及驗證流程的硬體加速器，即所稱的矽智財，來減少開發產品所需的時間，我們在這篇論文中提出了一個分層的平台整合方法，並選定目前最普遍被使用的進階微控制器匯流排架構(AMBA)來做為我們介面資料傳輸的標準，我們使用這個方法來將硬體加速器整合到一個以進階微控制器匯流排架構為基礎的系統單晶片上，工程師可藉由此方法整合硬體加速器到系統單晶片的平台上，而並不需要明白進階微控制器匯流排架構的規格，這種整合方法和以往只在平台上另行加入一個直接記憶體存取(DMA)模組來負責資料傳輸的方法相比，可以降低半數在匯流排上的資料傳輸，所以可以將資料傳輸的時間減半，如此一來可以得到更好的結果，我們並使用了JPEG解碼器整合離散餘弦函數轉換(Discrete Cosine Transform, DCT)硬體加速器和JPEG2000編碼器整合離散小波轉換(Discrete Wavelet Transform, DWT)硬體加速器及嵌入式區塊最佳化切割編碼(Embedded Block Coding with Optimized Truncation, EBCOT)硬體加速器來驗證所提出的方法。

System-on-chip (SOC) design relies on reuse of pre-designed and pre-varified hardware devices, also called intellectual properties (IPs). We choose the most popular on-chip bus standard, AMBA (Advanced Microcontroller Bus Architecture), as our communication interface protocol. We propose a kind of layered integration methodology to integrate IPs into AMBA-based SOC system. Engineers can follow the methodology to integrate IPs into AMBA-based SOC system without AMBA protocol know-how. This integration has better performance than DMA-based integration. The methodology reduces half of data transfer on bus compare with DMA. We demonstrate the proposed methodology with a JPEG decoder and a JPEG2000 encoder case.

ABSTRACT
CONTENTS
LIST OF FIGURES
LIST OF TABLES

CHAPTER 1.....1
INTRODUCTION
1.1 PLATFORM-BASED DESIGN AND IP REUSE
1.2 INTEGRATION OVERVIEW
1.3 PLATFORM AND DESIGN FLOW OVERVIEW
1.4 THESIS ORGANIZATION
CHAPTER 2.....7
PREVIOUS WORK
2.1 INTEGRATION METHODOLOGIES
2.2 IP INTEGRATION ARCHITECTURE
CHAPTER 3.....9
AMBA SPECIFICATION
3.1 INTRODUCTION OF AMBA
3.2 AMBA AHB
3.2.1 AMBA AHB Signal List
3.2.2 AHB Transfer Type
3.3 AHB DEVICE IMPLEMENTATION
3.3.1 AHB Slave Interface and FSM
3.3.2 AHB Master Interface and FSM
3.3.3 AHB DMA and FSM
CHAPTER 4.....22
PROPOSED INTEGRATION METHODOLOGY
4.1 APPLICATION LAYER
4.2 FUNCTION LAYER
4.3 IP ANALYSIS LAYER
4.3.1 IP Execution Requirements
4.3.2 IP Execution Cycle Estimation
4.3.3 IP Communicating Method
4.4 IMPLEMENTATION LAYER
4.4.1 Reusable Slave Interface
4.4.2 Reusable Master Interface
4.4.3 Software Driver
4.4.4 Control Logic
4.4.5 Modification for Platform Constraints
4.5 INTEGRATION LAYER
CHAPTER 5.....33
EXPERIMENTAL RESULT
5.1 INTEGRATION FOR DWT AND EBCOT TIER-1 IPS
5.2 SYNTHESIS REPORT
5.3 JPEG DECODER REPORT
5.4 DWT AND EBCOT TIER-1 REPORT
CHAPTER 6.....37
CONCLUSION
BIBLIOGRAPHY.....38

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