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研究生:蔡蒔修
研究生(外文):Shih-Hsiu Tsai
論文名稱:可組態乘法器之功率消耗估計模型
論文名稱(外文):Power Estimation Models for a Configurable Multiplier
指導教授:吳中浩
指導教授(外文):Allen C.-H. Wu
學位類別:碩士
校院名稱:國立清華大學
系所名稱:資訊工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2004
畢業學年度:92
語文別:英文
論文頁數:27
中文關鍵詞:功率估計乘法器
外文關鍵詞:Power estimationMultiplier
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  • 被引用被引用:0
  • 點閱點閱:136
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我們提出了一個可組態乘法器的功率消耗估計模型,這個估計模型可以預估各種不同組態的乘法器的功率消耗。我們提出的功率消耗模型中,特徵值抽取所需的運算資源被大幅度地減少。使用者可以將要輸入可組態乘法器的資料流,直接輸入到我們提出來的模型以得到估計的功率消耗,這個功率消耗估計模型可以在系統架構抽象層,幫助設計者針對乘法運算的功率消耗做最佳化的動作。我們提出的功率消耗估計模型在積體電路前期的設計階段就可以估計出可靠的功率消耗,大約有百分之三十二的錯誤率,而錯誤率的標準差是百分之十四左右。
We propose an architecture-level power estimation model for a configurable multiplier. The model can be automatically scaled with respect to different configurations of multiplier. Large amount of characterization effort is reduced. The user can directly feed the input sequences of a configurable multiplier to this model and derive the estimated average power consumption. This model can assist the designer to optimize the power consumption of multiplication operation at architecture-level abstraction. . The proposed model can efficiently estimate the power consumption at the early design stage, and yields average estimation errors around 32%. The standard deviation of the average error is around 14%.
[1] Subodh Gupta and Farid N. Najm, “Power Modeling for High-Level Power Estimation,” IEEE Trans. VLSI Systems, vol. 8, No. 1, Feb. 2000.
[2] Giuseppe Bernacchia and Marios C. Papaefthymiou. “Analytical Macromodeling for High-Level Power Estimation,” in Proceedings of IEEE International Conference on Computer Aided Design, Nov. 1999.
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[4] P. Duncan, S. Swamy, and R. Jain, “Low-power DSP circuit design using retimed maximally parallel architectures,” in Proc. 1st Symp. Integrated System, Mar. 1993, pp.266-275.
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[8] Subodh Gupta, Farid N. Najm, “Analytical Models for RTL Power Estimation of Combinational and Sequential Circuits,” Proc. of IEEE Alessandro Volta Memorial Workshop on Low-Power Design, 1999, Page 164.
[9] Michael Eiermann, Walter Stechele, “Novel Modeling Techniques for RTL Power Estimation”, International Symposium on Low Power Electronic Design, Aug. 2002. pp. 323-328
[10] Alessandro Bogliolo, Roberto Corgnati, Enrico Macii, Massimo Poncino, “Parameterized RTL Power Models for Soft Macros”, IEEE Trans. on VLSI Systems, vol. 9, No. 6, Dec. 2001, pp. 880-887.
[11] Paul E. Landman and Jan M. Rabaey, “Architectural Power Analysis: The Dual Bit Type Method”, IEEE Trans. on VLSI Systems, 1995, Pages173-187.
[12] Xun Liu Marios C. Papaefthymiou, “A Statistical Model of Input Glitch Propagation and its Application in Power Macromodeling”, Proc. of the 45th IEEE International Midwest Symposium on Circuits and Systems , August 2002
[13] Rita Yu Chen and Mary Jane Irwin, “Architecture-Level Power Estimation and Design Experiments”, ACM Transactions on Design Automation of Electronic Systems, Vol. 6, No. 1, January 2001, Pages 50-66.
[14] Alice Wang and Anantha P. Chandrakasan, “Energy-Aware Architectures for a Real-Valued FFT Implementation”, Proc. of ISLPED, 2003.
[15] Xun Liu and Marios C. Papaefthymiou, “A Markov Chain Sequence Generator for Power Macromodeling”, Proc. of ICCAD, 2003, Pages 404-411
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