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研究生:林立峯
研究生(外文):Li-Feng Lin
論文名稱:支援指令結構描述語言與GCC的結合技術
論文名稱(外文):Integrating ADL-family Languages into Machine Descriptions of GCC for Reconfigurable Processors
指導教授:李政崑
指導教授(外文):Jenq-Kuen Lee
學位類別:碩士
校院名稱:國立清華大學
系所名稱:資訊工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2004
畢業學年度:92
語文別:英文
論文頁數:53
中文關鍵詞:嵌入式系統Design space exploration架構描述語言可移植性編譯器GCC
外文關鍵詞:Embedded systemsDesign space explorationArchitecture description languagesRetargetable compilerGCC
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嵌入式系統已經被廣泛地應用在通訊、多媒體、電腦,甚至於資訊家電上,從早期使用 application specific integrated circuits
(ASIC),配合適當的軔體加以驅動,到目前已經有愈來愈多的高階產品,使用可程式化的 application specific integrated processor
(ASIP),除了效能更高,也能更有彈性地執行應用程式。隨著ASIP的應用,應用程式也多利用高階的C語言編寫,所以需要能夠把特定 ASIP 架構設計的效能發揮出來的編譯器,也因此編譯器成為整個嵌入式系統設計的關鍵軟體工具。

更進一步,對處理器架構設計者而言,在早期架構設計階段(design space exploration)要對不同的設計選擇作評估和取捨,包括了編譯器的軟體工具鏈(software toolchain)提供了低成本和高效率的評估平台,軟體工具鏈的產生直接影響架構開發所需的時間。為了提升設計的效率,並且避免應體設計的複雜度,新的設計方法使架構描述語言(ADL)來定義處理器的架構,而對應的軟體工具鏈則由電腦輔助設計系統自動產生。

本論文即是在探討由架構描述語言自動移植編譯器到新處理器的機制。我們使用開放源碼的 GNU C 編譯器來進行移植,一方面藉由比對架構描述語言與規則資料庫來產生GCC後端的標準指令模板,一方面抽取參數化的資訊建立相關的巨集和函式,並且希望透過適當的介面供使用者可以修改由此系統自動產生的GCC後端更進一步作最佳化。

這樣的機制不僅可以減輕ASIP編譯器設計的複雜度,也可以大幅增加處理器開發的效率。
Embedded systems have been widely applied in communication, multimedia, and many other fields such as consumer electronics. With the applying constraints on cost and power consumption, the requirement of short time-to-market, and the demand of performance, the adoption of high-end programable processors has become more common than ever. Traditionally application specific integrated circuits (ASIC) are no longer sufficient to satisfy the increasing needs.

Hence new methodology on design have evolved. Hardware/software co-design are taking places in order to optimize the design flow. The architecture description languages (ADL) of higher abstract levels are utilized to describe the behavior or structure of the processor. And computer automation tools are utilized to synthesize the hardware as well as to generate the software toolchain for design space exploration from the specification defined in the ADLs.

At design space exploration, various combinations of design
parameters are chosen and each is evaluated for the requirements applied from the specifications. Tradeoffs might be made during the many iterations in the design flow. The software toolchain is essential for this design process to enable the early evaluation of the design. A software toolchain contains a simulator, an assembler, and the linker. Also may be included are the debugger and the profiler. To evaluate the performance achievement on the target application, a compiler is certainly needed.

The implementing of the new software toolchain might cost many manpower and take a long development time. Hence an automation approach to generates the tools is desirable. Many efforts have been made to address on the various challenges and some solutions are achieved. However, we are not satisfied with the retarget compiler solutions.

There are two major expectations for the retargetable compilers for the design space exploration. First is that the code quality has to be acceptable otherwise the evaluation process could not yield convincible references. The other is that the retargeting process should be accomplished fast, i.e., in a few days. Even though the code quality is not comparable to the well-tuned compiler, it is still competitive since it does not required many months of work to adjust small modifications.

We choose to retarget the GNU C compiler (GCC) with the architecture description languages. We can benefit the already existing optimization mechanisms embedded in the compiler system to obtain acceptable code quality. The framework of the compiler architecture enables it comparable simpler to retarget new architectures. GCC is published under the GNU Public Licence and has been commonly accepted as a reference compiler system on many platforms.

Proposed in this thesis is a novel approach to generate GCC machine description (MD) from architecture specifications in the language of an ADL. It consists of two stages. First stage is the parsing of the ADL description codes into the GCC register transfer language (RTL), that is actually the intermediate representation of GCC compiler system. The second stage is the MD generation pass, which matches the parsed RTL with standard name patterns of GCC and produces the instruction patterns for GCC in the `.md' file. The core of the system consists of a database of instruction matching rules, which are constructed in three major ways: 1) collected from existing MDs of more than 40 architectures, 2) manually edited matching rules, and 3) inducted rules with other software suits. Besides, the machine parameters such as contained resources and pipeline constraints are analyzed and written into the GCC machine macros, the other part of the MD.

We hope this research can lead to the establishment of the interface of the transformation from the architecture description languages to the GNU C compiler, and contribute to the paradigm shift on the System-on-Chip (SoC) design methodology. Rather than being only a code generation system for a mature processor architecture, a compiler system has been a key component of the toolchains for the design space exploration.
Abstract i

Contents iv

List of Figures vi

List of Tables vii

1 Introduction 1
1.1 Background . . . . . . . . . . . . . . . . . . . . . 1
1.2 RelatedWork . . . . . . . . . . . . . . . . . . . . 3
1.2.1 Porting the GNU C compiler . . . . . . . . . . 3
1.2.2 Architectural description languages . . . . . 4
1.3 Thesis Overview . . . . . . . . . . . . . . . . . . 5

2 Architectural Description Languages 7
2.1 An ADL Overview . . . . . . . . . . . . . . . . . . 7
2.2 The LISA Processor Modeling Language . . . . . . . 12

3 The GNU C Compiler 15
3.1 Cross Compilation . . . . . . . . . . . . . . . . . 15
3.2 Building and Running GCC . . . . . . . . . . . . . 16
3.3 Compilation Passes . . . . . . . . . . . . . . . . 19
3.3.1 The compilation flow . . . . . . . . . . . . 19
3.3.2 The RTL generation pass . . . . . . . . . . . 21
3.3.3 The final pass and the insn matching . . . . 21
3.4 Machine Description . . . . . . . . . . . . . . . . 23
3.4.1 The `.md' file . . . . . . . . . . . . . . . 24
3.4.2 Target description macros . . . . . . . . . . 27

4 The ADL-to-MD Translator 29
4.1 Design Flow for the GCC Backend Generation . . . . 30
4.2 System Architecture . . . . . . . . . . . . . . . . 33

5 Applying Scenarios 39
5.1 Example for define_insn "mulsi3" . . . . . . . . . 40
5.2 Examples for define_expand "mulsi3" . . . . . . . . 42
5.3 Example for define_peephole2 . . . . . . . . . . . 45
5.4 Code Selection According to Cost Function . . . . . 46

6 Conclusion 47
6.1 Summary . . . . . . . . . . . . .. . . . . . . . . 47
6.2 Future Work . . . . . . . . . . . . . . . . . . . . 48

Bibliography 49
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