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研究生:閔紹恩
研究生(外文):Min Shawn
論文名稱:應用於W-CDMA之頻率合成器與其低功率壓控振盪器及注入鎖定式除頻器之實做
論文名稱(外文):Design and implementation of a voltage controlled oscillator and an injection locked frequency divider in the frequency synthesizers for W-CDMA application
指導教授:徐永珍徐永珍引用關係
指導教授(外文):Klaus Yung-Jane Hsu
學位類別:碩士
校院名稱:國立清華大學
系所名稱:電子工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2004
畢業學年度:92
語文別:中文
論文頁數:87
中文關鍵詞:WCDMA頻率合成器壓控振盪器除頻器相位雜訊
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本論文主要是根據3GPP(3rd Generation Partner-ship Project)的機構所制訂的WCDMA規格,在直接降頻(Direct-Conversion)接收器的架構下,針對其接收端頻段:2110MHz~2170MHz,以及本地振盪源在8Mhz偏移主頻處相位雜訊<-130dBc/Hz之要求,進行設計,模擬並且實做工作在兩倍射頻頻率的壓控振盪器,以及低消耗功率的注入鎖定式除二除頻器,將本地振盪源設計在兩倍的射頻頻率再降頻,主要是要降低直接降頻式接收器的本地振盪源經由電容,基板及打線路徑耦合,洩漏至混頻器射頻端,或是洩漏至低雜訊放大器放大再經由混頻器自我混頻所造成的直流準位漂移,故在製程變異以及電壓擾動下,所設計的壓控振盪器均須能夠振盪在4.22Ghz~4.34Ghz,且相位雜訊換算成在1Mhz偏移主頻處需小於-115dBc/Hz
所設計模擬的壓控振盪器,以及除二除頻器是採用台積電0.18um,1P6M的RFCMOS製程,壓控振盪器可調範圍為:4.164~4.382GHz,核心電路消耗電流為3.04mA,相位雜訊在1Mhz偏移主頻處為-119~-113dBc,注入鎖定式除頻器核心電路消耗電流為0.426mA,透過追蹤鎖定的方式,除頻器的除頻範圍大約有1000MHz,晶片面積約為1100um*1100um,經過On wafer的量測後,壓控振盪器有大約150MHz的頻率飄移,可調範圍大約為: 4.365~4.505GHz,經除頻器降頻後,相位雜訊在1Mhz偏移主頻處為:-117~-115dBc。
本論文同時利用Matlab模擬了整數型鎖相迴路的鎖定時間,頻寬,迴路雜訊的來源,以及利用H-spice來模擬鎖相迴路中,相位頻率比較器(PFD),電荷幫浦(Charge Pump),前置除頻器(Pre-scaler),程式計數器(Program Counter )以及屏蔽計數器(Swallow Counter)等電路。
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