跳到主要內容

臺灣博碩士論文加值系統

(34.226.244.254) 您好!臺灣時間:2021/08/01 01:42
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果 :::

詳目顯示

我願授權國圖
: 
twitterline
研究生:陳信宏
研究生(外文):Hsin-Hon Chen
論文名稱:數位化交直流轉換器之功率因數校正電路
論文名稱(外文):Digital power factor correction circuit of AC/DC converter
指導教授:龔正龔正引用關係
指導教授(外文):Jeng Gong
學位類別:碩士
校院名稱:國立清華大學
系所名稱:電子工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2004
畢業學年度:92
語文別:中文
論文頁數:111
中文關鍵詞:功率因數交直流轉換器數位式
外文關鍵詞:PFAC/DCdigital
相關次數:
  • 被引用被引用:0
  • 點閱點閱:150
  • 評分評分:
  • 下載下載:0
  • 收藏至我的研究室書目清單書目收藏:0
這篇論文介紹一些電源轉換器的型式和功因校正電路的機制,並且對之前的一些論文加以研究,最後展現利用TSMC CMOS 0.35 �慆 製程參數去實現數位的功因校正電路。
隨著超大型積體電路設計(VLSI)技術的成長,工業和電子產品都需要可靠、便宜和有智慧的電力控制系統。如何控制幾瓦甚至幾千瓦的電力轉換,且在轉換中不損耗太多的能量變成學者研究的焦點。換句話說,如何有效的利用能量,變成電力電子中的一個目標。而功因校正電路在改善使用效率和降低電源污染扮演一個很重要的角色。當人們開始注意環境保護的同時,有些人也開始去關切電力系統的污染問題。很多在歐洲和北美洲的國家也制訂相關標準去對一些電力產品做限制,如IEEE 519和IEC 1000-3-6等規則。功因校正電路因為可以達到比較高的功率因數且可以減少總諧波失真,所以在現今很多的電力產品都會附加功因校正的功能。
現在很多IC設計的觀念都源自於數位和類比電路,這兩種系統也都分別有各自的優缺點。而現在的功因校正電路也是分成類比和數位兩大類。這篇論文將比較這兩種功因正電路的優缺點,並結合兩者的部分優點去實現功因校正電路。因為這裡的功因校正電路大部分還是由數位的方塊組成,所以這個功因校正電路仍稱為數位功因校正電路。最後在此會使用TSMC CMOS 0.35 �慆 製程參數去模擬電路,並完成功率因數為0.999,且全載時總諧波失真為2.09%,同時符合IEC及IEEE等的國際標準。
This thesis introduces some type of the power converters and themechanism of power factor correction (PFC) circuits; and present the study and implementation of digital power factor correction circuit that uses TSMCCMOS 0.35 um technology to realize PFC circuit.

With the growing of VLSI technology, the development of industry and electronic products all need more reliable, cheap and intelligent power control system. How to control several watts even tens of kilowatts power transformation without consuming too much energy during transforming is the topic for scholars to study and implementation. In the other word, how to use energy efficiently will be an aim to power electronics. PFC circuits play an important role to improve the efficiency and to minimize the power pollution .When people pay attention to environmental protection, some people also care about the pollution about power system. Many countries in Europe and North America make some standards to constrain some power products, IEEE 519 and IEC 1000-3-6 for example. PFC circuit can achieve high power correction factor and minimize the total harmonic distortion, so nowadays many powerproducts include the PFC function in them.

Many IC design concepts base on digital and analog circuits , these two types both have advantages and disadvantages. The PFC circuits are also divided into two types---digital and analog. This thesis will compare these two types, and combine some advantages of digital and analog circuits to realize the PFC circuit. Because the majority of the PFC circuit is digital, it still called ‘digital PFC circuit’. Finally, this work uses TSMC CMOS 0.35 um technology to simulate PFC circuit, then the power factor achieves 0.999 and total harmonic distortion achieves 2.09% when full loading.
[1] Fu, M.; Chen, Q.,” A DSP based controller for power factor correction (PFC) in a rectifier circuit,” Applied Power Electronics Conference and Exposition, 2001. APEC 2001. Sixteenth Annual IEEE , Volume: 1 , 4-8 March 2001 Pages:144 - 149 vol.1.

[2] Wanfeng Zhang; Guang Feng; Yan-Fei Liu; Bin Wu,” A new power factor correction (PFC) control method suitable for low cost DSP,” Telecommunications Energy Conference, 2002. INTELEC. 24th Annual International , 29 Sept.-3 Oct. 2002 Pages:407 – 414.

[3] Yu Qin; Shanshan Du,” A novel adaptive hysteresis band current control using a DSP for a power factor corrected on-line UPS,” Industrial Electronics, Control and Instrumentation, 1997. IECON 97. 23rd International Conference on , Volume: 1 , 9-14 Nov. 1997 Pages:208 - 212 vol.1.

[4] Van de Sype, D.M.; De Gusseme, K.; Van den Bossche, A.P.; Melkebeek, J.A,” A sampling algorithm for digitally controlled boost PFC converters,” Power Electronics Specialists Conference, 2002. pesc 02. 2002 IEEE 33rd Annual , Volume: 4 , 23-27 June 2002 Pages:1693 – 1698.

[5] Gyeong-Hae Han; Bum-Suk Ko,” All-digital logic control PWM/PFC for inverter system,” Electronics, Circuits and Systems, 2000. ICECS 2000. The 7th IEEE International Conference on , Volume: 2 , 17-20 Dec. 2000 Pages:789 - 792 vol.2.

[6] Ulhaq, S.M.; Shirakawa, S.; Nakaoka, M.; Takano, H,” Computer-aided simulation of digitally-controlled active single phase PFC converter,” Power Electronics and Variable Speed Drives, 1998. Seventh International Conference on (IEE Conf. Publ. No. 456) , 21-23 Sept. 1998 Pages:121 – 126.

[7] de Castro, A.; Zumel, P.; Garcia, O.; Riesgo, T.; Uceda, J,” Concurrent and simple digital controller of an AC/DC converter with power factor correction based on an FPGA,” Power Electronics, IEEE Transactions on , Volume: 18 , Issue: 1 , Jan. 2003 Pages:334 – 343.

[8] De Gusseme, K.; Van de Sype, D.M.; Melkebeek, J.A.A,” Design issues for digital control of boost power factor correction converters,” Industrial Electronics, 2002. ISIE 2002. Proceedings of the 2002 IEEE International Symposium on , Volume: 3 , 26-29 May 2002 Pages:731 - 736 vol.3.

[9] Ya-Tsung Feng; Gow-Long Tsai; Ying-Yu Tzou,” Digital control of a single-stage single-switch flyback PFC AC/DC converter with fast dynamic response,” Power Electronics Specialists Conference, 2001. PESC. 2001 IEEE 32nd Annual , Volume: 2 , 17-21 June 2001 Pages:1251 - 1256 vol.2.

[10] Mobin, S.; Hiraki, E.; Takano, H.; Nakaoka, M.,” Simulation method for DSP-controlled active PFC high-frequency power converters,” Electric Power Applications, IEE Proceedings- , Volume: 147 , Issue: 3 , May 2000 Pages:159 – 166.

[11] Robert W. Erickson, Dragan Maksimoic’,”fundamentals of power electronics second edition,”Kluewr Academic Publishers, 2001.

[12] Mohan, Undeland, Robbins,”Power Electronics”3rd edition, John Wiley& Sons, Inc. 2003.

[13] Wilsun Xu, “Comparisons and comments on harmonic standards IEC 1000-3-6 and IEEE Std. 519”, Harmonics and Quality of Power, 2000. Proceedings. Ninth International Conference on , Volume: 1 , 1-4 Oct. 2000 Pages:260 - 263 vol.1.

[14] F.C. Lee, P. Barbosa, X. Peng, J. Zhang, B. Yang and F. Canales,“Topologies and design considerations for distributed power system applications,” Proceedings of the IEEE, issue 6, June 2001, vol. 89, pp. 939 –950.

[15] 王信雄博士, “高等電力專題,”Lecture note, Fall, 2003 .

[16] A. Prasad, P Ziogas, S Manias “A Novel Passive Wave shaping Method for Single-Phase Diod Rectifiers” IEEE Transaction on Industrial Electronics, VOL 37, NO 6, December 1990, P521-30.

[17] R. Redl, L. Balogh “Power-Factor Correction in Bridge and Voltage-Doubler Rectifier Circuits with Inductor and Capacitors” APEC’95, P446-72.

[18] P. Parto and K. Smedley, "PASSIVE PFC FOR FLYBACK CONVERTORS." International Power Conversion and Intelligent Motion Conference (PCIM 99), Chicago.

[19] C. Qiao and K. Smedley, "Improved Integration Control of Power Factor Correction" IEEE Industrial Electronics Conference (IECON), Nov. 1999.

[20] Zaohong Yang and P.C. Sen, ”Recent Developments In High Power Factor Switch-mode Converters” Electrical and Computer Engineering, 1998. IEEE Canadian Conference on Volume:2, 1998, Page(2):477-480 vol.2 .

[21]鄭全宏, ”應用數位信號處理器建構之並聯市電換流器,” 國立成功大學電機工程研究所碩士論文,” 民國87年.

[22] Sangsun Kim and Dr. P. Enjeti, ”Digital Control of Switching Power Supply – Power Factor Correction Stage,” Power Electronics of Electrical Engineering, Texas A&M University.

[23] Tanitteerapan, T.; Mori, S.,” An input current shaping technique for PFC flyback rectifier by using inductor voltage detection control method,” Electrical and Electronic Technology, 2001. TENCON. Proceedings of IEEE Region 10 International Conference on , Volume: 2 , 19-22 Aug. 2001 Pages:799 - 803 vol.2.

[24] Wang, Z.,” A CMOS four-quadrant analog multiplier with single-ended voltage output and improved temperature performance,” Solid-State Circuits, IEEE Journal of , Volume: 26 , Issue: 9 , Sept. 1991 Pages:1293 – 1301.

[25] Maundy, B.; Maini, M.,” Correction to "A comparison of three multipliers based on the technique for low-voltage applications",” Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on [see also Circuits and Systems I: Regular Papers, IEEE Transactions on] , Volume: 50 , Issue: 10 , Oct. 2003 Pages:1370 – 1370.

[26] Enomoto, T.; Yasumoto, M.-A.,” Integrated MOS four-quadrant analog multiplier using switched capacitor technology for analog signal processor ICs,” Solid-State Circuits, IEEE Journal of , Volume: 20 , Issue: 4 , Aug 1985 Pages:852 – 859.

[27]林世宏,”電子安定器積體電路研製,” 清華大學電機工程研究所碩士論文, 民國86年6月.

[28] Martin Rowe,” How do ADCs work?,” Test & Measurement World, July 2002.

[29] Lin, Y.-M.; Kim, B.; Gray, P.R.,” A 13-b 2.5-MHz self-calibrated pipelined A/D converter in 3-μm CMOS,” Solid-State Circuits, IEEE Journal of , Volume: 26 , Issue: 4 , April 1991 Pages:628 – 636.

[30] Dae Yong Kim, Gil Su Kim, Hoon Jae Ki, and Soo Won Kim,” 2.5 V, 10-bit, 50-MS/s CMOS Pipeline Low Power A/D Converter,” ASIC Design Lab., Dept. of Electronics Eng., Korea Univ.

[31] Kannan Sockalingam and Rick Thibodeau,” 10-Bit 5MHz Pipeline A/D Converter,” July 30, 2002.

[32] Yotsuyanagi, M.; Etoh, T.; Hirata, K.,” A 10 b 50 MHz pipelined CMOS A/D converter with S/H,” Solid-State Circuits, IEEE Journal of , Volume: 28 , Issue: 3 , March 1993 Pages:292 – 300.

[34] Cho, T.B.; Gray, P.R..” A 10 b, 20 Msample/s, 35 mW pipeline A/D converter,” Solid-State Circuits, IEEE Journal of , Volume: 30 , Issue: 3 , March 1995 Pages:166 – 172.

[35] Toshio Kumamoto, Osamu Matsumoto, Masao Ito, Takashi Okuda,Hiroyuki Momono*, Takahiro Miki, Keisuke Okada and Tadashi Sumi,” A 10-bit 50MS/s 300mW A/D Converter using Reference Feed-Forward Architecture,” System LSI Laboratory *Manufacturing Technology Division, Mitsubishi Electric Corporation 4-1 Mizuhara, Itami, Hyogo 664, Japan.

[36] Behzad Razavi,” Design of Analog CMOS Integrated Circuits,” McGraw-Hall Higher Education, 2001.

[37] Lee, G.B.; Chan, P.K.; Siek, L,” A CMOS phase frequency detector for charge pump phase-locked loop,” Circuits and Systems, 1999. 42nd Midwest Symposium on , Volume: 2 , 8-11 Aug. 1999 Pages:601 - 604 vol. 2.

[38] Kuo-Hsing Cheng; Tse-Hua Yao; Shu-Yu Jiang; Wei-Bin Yang,” A difference detector PFD for low jitter PLL,” Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on , Volume: 1 , 2-5 Sept. 2001 Pages:43 - 46 vol.1.

[39] Hee-Tae Ahn; Allstot, D.J.,” A low-jitter 1.9-V CMOS PLL for UltraSPARC microprocessor applications,” Solid-State Circuits, IEEE Journal of , Volume: 35 , Issue: 3 , March 2000 Pages:450 – 454.

[40] Johansson, H.O.,” A simple precharged CMOS phase frequency detector,” Solid-State Circuits, IEEE Journal of , Volume: 33 , Issue: 2 , Feb. 1998 Pages:295 – 299.

[41] Ya-Chin King,”Analog Circuit Design,”Lecture notes, chapter 7, Fall 2001.

[42] Liang Dai; Harjani, R.,” CMOS switched-op-amp-based sample-and-hold circuit,” Solid-State Circuits, IEEE Journal of , Volume: 35 , Issue: 1 , Jan. 2000 Pages:109 – 113.

[43] Yin, G.M.; Eynde, F.O.; Sansen, W.,” A high-speed CMOS comparator with 8-b resolution,” Solid-State Circuits, IEEE Journal of , Volume: 27 , Issue: 2 , Feb. 1992 Pages:208 – 211.

[44] Daegyu Lee, Jincheol Yoo, Kyusun Choi, and Jahan Ghaznavi, ”Fat Tree Encoder Design For Ultra-High Speed Flash A/D Converters,” Circuits and Systems, 2002. MWSCAS-2002. The 2002 45th Midwest Symposium on , Volume: 2 , 4-7 Aug. 2002 Pages:II-87 - II-90 vol.2.

[45] Pereira, P.; Fernandes, J.R.; Silva, M.M.,” Wallace tree encoding in folding and interpolation ADCs,” Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on , Volume: 1 , 26-29 May 2002 Pages:I-509 - I-512 vol.1.

[46] Shi-Yu Huang, ”VLSI Design,” 2003.Spring,Leture note, Chapter 8.
QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top