臺灣博碩士論文加值系統

我們成功的製備金屬（Al）/氧化鑭（La2O3）/半導體（p-Si）結構的電容器，並對元件作基本的變溫電性量測，溫度範圍在300 K至470 K，所得到的結果顯示絕緣層厚度為18 nm，經過快速熱退火500 0C通氮氣60秒後，在溫度470 K電場為2.25 MV/cm 以下時，Al/ La2O3界面間的電流傳導機制為蕭基發射所主導,所得到的Al/ La2O3的蕭基能帶高為0.95 eV。而絕緣層厚度為24 nm，經過快速熱退火700 0C通氮氣60秒後，發現電流機制為空間電荷限制電流所主導，Von 是 0.08 V，VTFL 是 0.3 V，缺陷能階在傳導帶下方0.21 eV，氧化鑭薄膜內的電子遷移率在溫度300 K時是8.15´10-7 cm2/V-sec。
當氧化鑭薄膜的厚度為24 nm，介電常數為16。至於材料物性方面，我們也作了Secondary Ion Mass Spectrometry (SIMS)、X-Ray Diffraction (XRD)、X-ray Photoelectron Spectroscopy (XPS)、TEM等分析，亦有了些許的收穫，由SIMS我們發現La和Si會有互相擴散的現象，而經由XRD的結果分析我們發現當氧化鑭薄膜經過快速熱退火700 0C後，薄膜有了結晶的現象。由TEM我們發現在氧化鑭薄膜和矽基板間有一層厚度約3.5 nm的介面層，此介面曾經由XPS的結果分析證明是La的矽酸鹽(silicate)。
本實驗中，我們成功地製作了N通道的金屬（Al）/氧化鑭（La2O3）/半導體（p-Si）的場效電晶體，我們使用射頻磁控濺鍍法沈積La2O3薄膜，在基本電性上的表現，如：ID-VD，ID-VG及C-V等，皆證明電晶體能夠正常的操作，且發現臨界電壓約在-1.0V，最小的次臨界斜率是167 mV/dec.，在VD=0.1V下，ION/IOFF的比例有5個數量級之多，顯示電晶體有不錯的電流切換能力。經由次臨界斜率St=2.3(kT/q)[1+(CD+Cit)/Cox]的計算，可以得到界面缺陷電荷密度（Dit）為5.42x1012 cm-2-eV-1。

Metal-oxide-semiconductor (MOS) capacitors that incorporate La2O3 dielectrics were fabricated by RF magnetron sputtering. In this work, the essential structures and electrical properties of La2O3 thin film were investigated. C-V, X-ray energy dispersive spectrometer (EDS) and TEM analyses reveal that an interfacial layer was formed, reducing the κ-value of the annealed La2O3 thin films. The conduction mechanisms of the Al/La2O3 (24 nm)/p-Si metal-lanthanide oxide-semiconductor structure were also studied. The J-V characteristics of the MOS capacitors in accumulation showed the behavior of space charge limited conduction with traps. Three different regions, namely Ohm’s law, trap filled limited and Child’s law were explicitly observed in J-E characteristics at room temperature. The activation energy in the trap filled limited region calculated from the Arrhenius plots was about 0.21±0.01 eV. This energy was attributed to the shallow traps, distributed near the conduction band edge in the forbidden gap of La2O3. The electronic mobility, trap density, dielectric relaxation time and density of states in conduction band were determined from the space charge limited currents at room temperature. The dielectric constant measured from a separate metal- La2O3-silicon capacitors is 16.

At high temperature (470 K) and low field (≦2.25 MV/cm), the conduction mechanisms of the Al/La2O3 (18 nm)/p-Si metal-lanthanide oxide-semiconductor structure was studied to be Schottky emission. And barrier height of Al/La2O3 of 0.95 eV is deduced. The band diagram of the Al/La2O3 /p-Si metal-lanthanide oxide-semiconductor structure was also constructed.

N-channel metal-oxide-semiconductor field effect transistors (MOSFETs) using La2O3 gate oxide were fabricated successfully. The La2O3 films were deposited by RF magnetron sputtering. The C-V, ID-VD and ID–VG characteristics are measured. The threshold voltage was -1.0 V. The subthreshold swing was 167 mV/dec. The ION/IOFF ratio is about 105 at VD=0.1 V. Since St=2.3(kT/q)[1+(CD+Cit)/Cox], the interface trapped charge density Dit is extracted to be about 5.42x1012 cm-2-eV-1.

第一章 緒論………………………………………………………………1
1.1 高介電常數（High-κ）薄膜於極大型積體電路（ULSI）的發展1
1.2 High-κ薄膜在DRAM上的應用………………………………………2
1.3 High-κ薄膜於MOSFET閘極氧化層（Gate Oxide）的發展………3
1.4 La2O3薄膜的製備方法………………………………………………3
1.5 本論文的研究方向…………………………………………………4
第二章 熱穩定性（Thermodynamic Stability）之探討……………6
2.1 「熱穩定性」理論簡介……………………………………………6
2.2 矽化物（Silicide）及矽酸鹽（Silicate）的產生……………7
第三章 La2O3（氧化鑭）薄膜元件的製備……………………………9
3.1 射頻磁控濺鍍法（RF Magnetron Sputtering）的簡介…………9
3.2 晶片背面歐姆接面（Ohmic contact）的製備…………………10
3.3 La2O3薄膜的成長…………………………………………………10
3.4 La2O3薄膜電容器的製備…………………………………………11
3.5 La2O3薄膜電晶體的製備…………………………………………11
3.6 量測使用儀器………………………………………………………14
第四章 La2O3薄膜基本介紹及物性量測分析…………………………15
4.1 La2O3薄膜的基本介紹……………………………………………15
4.2 二次離子質譜儀（SIMS）縱深分佈之分析………………………15
4.3 X-Ray 繞射分析……………………………………………………16
4.4電子能譜儀(E.S.C.A.)之分析……………………………………17
4.5穿隧式電子顯微鏡（TEM）照相分析………………………………18
第五章 Al/ La2O3/Silicon電容器基本電性及漏電流機制分析……19
5.1 I-V（電流-電壓）特性曲線量測…………………………………19
5.2 C-V (電容-電壓) 特性曲線量測…………………………………19
5.3 漏電流傳導機制之簡介……………………………………………20
5.3.1 蕭基發射（Schottky emission）…………………………21
5.3.2 普爾-法蘭克發射（Poole-Frenkel Emission）…………22
5.3.3 傅勒-諾德翰穿隧（Fowler-Nordheim Tunneling）……23
5.3.4 歐姆傳導（Ohmic Conduction）…………………………24
5.3.5空間電荷限制電流(space charge limited current, SCLC)………24
5.4 MIS結構電容器與溫度變化之漏電流傳導機制分析……………26
5.5 本章結論……………………………………………………………30
第六章 Al/La2O3/Silicon場效電晶體基本電性量測………………31
6.1 IDS-VDS Curve的特性探討………………………………………31
6.2 IDS-VGS Curve的特性探討………………………………………32
6.3 次臨界斜率（Sub-threshold Swing）…………………………32
6.4 臨界電壓（VT）的粹取……………………………………………33
6.5 遷移率（Mobility）的探討………………………………………34
第七章 結論……………………………………………………………37
參考資料…………………………………………………………………39
實驗圖表…………………………………….…………………………42
附錄……………………………………………………………………79
電晶體製程之三道光罩圖………………………………………………79

[1] H. S. Momose, M. Ono, T. Yoshitomi, T. Ohguro, S. Makamura, M. Saito, and H. Iwai, “1.5 nm direct-tunneling gate oxide Si MOSFET’s,” IEEE Trans. Electron Devices, vol. 43, pp. 1233–1241, August 1996.
[2] J. L. Autran, R. Devine, C. Chaneliere, and B. Balland, “Fabrication and characterization of Si-MOSFET’s with PECVD amorphous Ta2O5 gate insulator,” IEEE Electron Device Lett., vol. 18, pp. 447–449, September 1997.
[3] C. Chaneliere, S. Four, J. L. Autran, R. A. B. Devine, and N. P. Sandler, “Properties of amorphous and crystalline Ta2O5 thin films deposited on Si from Ta(OC2H5)5 precursor,” J. Appl. Phys., vol. 83, no. 9, pp. 4823-4829, May 1998.
[4] Q. Lu, D. Park, A. Kalnitsky, C. Chang, C. C. Cheng, S. P. Tay, T. J. King, and C. Hu, “Leakage Current Comparison Between Ultra-Thin Ta2O5 Films and Conventional Gate Dielectrics,” IEEE Electron Device Lett., vol. 19, no. 9, pp. 341-342, September 1998.
[5] D. Park, Y. King, Q. Lu, T. J. King, C. Hu, A. Kalnitsky, S. P. Tay, and C. C. Cheng, “Transistor Characterization with Ta2O5 Gate Dielectric,” IEEE Electron Device Lett., vol. 19, no. 11, pp. 441-443, November 1998.
[6] B. C. Lai, N. Kung, and J. Y. Lee, “A study on the capacitance-voltage characteristics of metal-Ta2O5-silicon capacitors for very large scale integration metal-oxide-semiconductor gate oxide applications,” J. Appl. Phys., vol. 85, no. 8, pp. 4087-4090, April 1999.
[7] J. C. Yu, B. C. Lai, and J. Y. Lee, “Fabrication and Characterization of Metal-Oxide-Semiconductor Field-Effect Transistors and Gated Diodes Using Ta2O5 Gate Oxide,” IEEE Electron Device Lett., vol. 21, no. 11, pp. 537-539, November 2000.
[8] B. C. Lai, J. C. Yu, and J. Y. Lee, “Ta2O5/Silicon Barrier Height Measured from MOSFETs Fabrication with Ta2O5 Gated Dielectric,” IEEE Electron Device Lett., vol. 22, no. 5, pp. 221-223, May 2001.
[9] Y.H.Wu, Alber Chin, “Electrical Characteristics of High Quality La2O3 Gate Dielectric with Equivalent Oxide Thickness of 5 Ả,” IEEE Electron Device Lett., vol. 21, no. 7, pp.341-343, July 2000.
[10] J. R. Hauser, Tech. Dig. Int. Electron Device Meeting, Short Course on Sub-100nm CMOS, IEEE, Piscataway, NJ, 1999.
[11] M. Jason Kelly, D. B. Terry, “Properties of La-silicate high-K dielectric films formed by oxidation of La on silicon,” J. Appl. Phys., vol. 93, pp. 1691-1696, February 2003.
[12] J. H. Jun, C. H. Wang, D. J. Won, “Structural and Electrical Properties of a La2O3 Thin Film as a Gate Dielectric,” Journal of the Korea Physical Society, vol. 41, no. 6, pp. 1-5, December 2002.
[13] S.Ohmi, C. Kobayashi, “Characterization of La2O3 and Yb2O3 Thin Films for High-K Gate Insulator Application,” Journal of Electrochemical Society, vol. 150, no. 7, pp. F134-F140, 2003.
[14] Iwai, H. Ohmi, S. Akama, S. Ohshima, C. Kikuchi, A. Kashiwagi, I. Taguchi, J. Yamamoto, H. Tonotani, J. Kim, Y. Ueda, I. Kuriyama, A. Yoshihara, “Advanced gate dielectric materials for sub-100 nm CMOS,” Electron Devices Meeting, 2002., International, 8-11, pp.625-628, December 2002.
[15] Y. Kim, A. Kuriyama, Isao Ueda, S. Ohmi, K. Tsutsui and H. Iwai, “Analysis of Electrical Characteristics of La2O3 Thin Films Annealed in Vacuum and Others,” European Solid-State Device Research Conference, 2003, vol. 16, pp. 569-572, 2003.
[16] K. J. Hubbar and D.G. Schlom, “Thermodynamic stability of binary oxides in contact with silicon,” J. Mater. Res., vol. 11, no. 11, pp. 2757-2776, November 1996.
[17] S. Lee et al., “High Quality Ultra Thin CVD HfO2 Gate Stack with Poly-Si Gate Electrode,” IEEE Symposium on VLSI Technology Digest of Technical Papers, ” pp. 31-34, 2000.
[18] S. M. Sze, Physics of Semiconductor Device, 2nd ed., Wiley, New York, 1981.
[19] D. K. Schroder, Semiconductor Material and Device Characteristics, Wiley, Arizona, 1998.
[20] K.C. Kao, and W. Hwang, Electrical Transport in Solids, Pergamon, New York, 1981.
[21] P. Mark, and W. Helfrich, “Space-Charge-Limited Currents in Organic Crystals,” J. Appl. Phys. vol. 33, p.205 1965.
[22] M.A. Lampert and P. Mark, Current Injection in Solids, Academic, New York, 1970.
[23] M.A. Lampert, “Simplified Theory of Space-Charge-Limited Currents in an Insulator with Traps,” Phys. Rev., vol. 103, p.1648, 1956.
[24] K. Chen, H. C. Wann, J. Dunster, P. K. Ko, and C. Hu, “MOSFET Carrier Mobility Model Based on Gate Oxide Thickness, Threshold Voltage and Gate Voltages,” Solid-State Electronics, vol. 39, no. 10, pp. 1515-1518, 1996.
[25] D. K. Schroder, Semiconductor Material and Device Characteristics, Wiley, Arizona, 1998.