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研究生:蘇炳誠
研究生(外文):Ping-Cheng Su
論文名稱:5.2GHzCMOS射頻前端電路設計
論文名稱(外文):The design of 5.2 GHz CMOS RF front-end circuit
指導教授:龔 正
指導教授(外文):J. Gong
學位類別:碩士
校院名稱:國立清華大學
系所名稱:電子工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2004
畢業學年度:92
語文別:中文
論文頁數:90
中文關鍵詞:低雜訊放大器壓控震盪器混頻器RFCMOS射頻前端電路
相關次數:
  • 被引用被引用:0
  • 點閱點閱:161
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  • 下載下載:0
  • 收藏至我的研究室書目清單書目收藏:2
在本論文裡,我們設計以TSMC 0.18um RF CMOS 製程為基礎的射頻前端電路區塊,它包括:低雜訊放大器(LNA),壓控震盪器(VCO),混頻器(mixer)等電路,其中LNA以共源極電感退化式放大器為架構,VCO的架構為互補式cross-coupled式架構,混頻器則選擇以主動式Gilbert cell混頻器為主。在電路規格上,所有設計的輸出皆符合IEEE 802.11a WLAN的規範,有些IEEE 802.11a WLAN規格所沒有明確的規範,將以參考其它論文所訂之規格為主。電路區塊輸入射頻(RF)頻率為5.2 GHz,本地震盪(LO)器的頻率為5.0GHz,中頻輸出頻率為200MHz。在電路模擬過程上以ADS 射頻軟體進行,並且以 ASITIC 電感模型取代TSMC無法提供的特殊規格電感模型。考量製程上飄移因素,模擬中以TSMC corner case進行電路模擬,使電路在最惡劣的製程環境下,所設計的功能仍能符合我們所訂的規格。個別電路模擬所得的重要結果有:低雜訊放大器S11 為-15.87dB ,NF (50Ω)為2.29 dB,混頻器(mixer)的IIP3為-0.05 dB,轉換增益為-0.23dB,壓控震盪器的相位雜訊(1MHz offset frequency)為-109.4 dB,其中壓控震盪器為了避免負載效應與基板洩漏的效應,在混波器與壓控震盪器之間插入一個緩衝器電路以增加埠與埠隔離度。最後將個別電路加以整合,形成我們所要的核心區塊,整體電路的重要輸出結果有:S11參數為-13.75dB,轉換增益為19.93dB ,NF (50Ω)為4.69 dB,IIP3為-16.94 dB,整體功率消耗為46.46mW。最後所有的輸出結果皆符合IEEE 802.11a WLAN所規範規格,無論在任何 製程飄移的corner case下。
In this thesis, we design a radio-frequency front-end circuit block base on TSMC 0.18um RF CMOS process model. The circuit includes low-noise amplifier (LNA), voltage-controlled oscillator (VCO) and mixer. The LNA frame is the common-source with inductive degeneration LNA, VCO is complementary cross-coupled pair structure, and mixer structure is the active Gilbert cell. The output specifications of the designed circuit blocks follow the IEEE 802.11a WLAN specifications. Some specifications except IEEE 802.11a WLAN specifications reference to other papers or researches. The input RF frequency of our designed blocks is 5.2 GHz , LO output frequency is 5.0 GHz, and IF output frequency is 200 MHz. We use ADS RF software to simulate the circuit, and use ASITIC inductor model to design inductors that are not involved in TSMC model. Considering about the process variation, we simulate circuit with corner cases supported by TSMC model to verify our design. The independent unit circuit important output results are listed as the following : The LNA S11 is -15.87 dB, NF is 2.29dB , mixer IIP3 is -0.05dB, conversion gain is -0.23dB, and the VCO phase noise is -109.4 dB at 1MHz offset frequency. In order to avoid the substrate feed-through and loading effect, we insert a buffer circuit between VCO and mixer to increase the port to port isolation. Finally, we merge all independent units to form the core circuit blocks that we wanted. The block circuit output results are: S11 is-13.75 dB, conversion gain is 19.93dB, NF (50Ω) is 4.69 dB, IIP3 is 16.94 dB, and of the entire circuit power consumption is 46.46mW. The final output result is conformed to IEEE 802.11a WLAN specification at all corner cases.
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