臺灣博碩士論文加值系統

矽智產與記憶體核心是矽統晶片（System-on-Chip---SOC）的兩大主要元件，然而矽智產的再利用衍生出許多測試整合上的困難與挑戰。此外，在系統晶片中，大量且不同種類組成的記憶體，同樣增加了測試的成本。這兩個問題使得測試成本，尤其是在測試整合方面，成為系統晶片發展過程中的主要成本。如何降低數位邏輯元件以及記憶體的測試成本是系統晶片發展必須要考量的一個重要課題。

在系統晶片測試方面，儘管已經有很多人致力於的各主題單方面的研究，但是卻鮮少有相關的研究討論測試整合實際的問題，在本篇文章中，我們考慮了各方面的問題，提出一個整合型的解決方案。所提出的測試存取控制系統（Test Access Control System---TACS）可以解決測試整合的問題。基於國際電機工程師協會（IEEE）編號P1500的標準，我們也提出了一個有彈性的測試存取機制（Test Access mechanism---TAM），以及測試控制器（Test Controller）。同時發展出一個系統晶片的測試整合平台---SOC Test Aid Console，簡稱STEAC，可以讓系統晶片的測試整合達到自動化。所提出的測試架構（TACS）跟整合平台（STEAC）除了解決了矽智產測試再利用的問題，同時也解決了整合過程中實際遇到的問題，包含測試排程、如何減少測試I/O、功能形測試樣形、I/O分享的問題等。基於我們提出的測試架構跟測試存取機制，提出了新的測試排程模型，除了與先前的研究一樣有考慮功率消耗的限制外，也考慮的I/O資源的限制。精確的模型使得測試排程可以找到一個比較好的結果，降低整體的測試時間。同時提出的架構可以同時支援scan跟功能形測試樣形。整個架構實際應用在一個工業界的系統晶片，成功的完成測試整合。從設計的經驗以及模擬的結果來看，我們的方法簡單而且有效率，可以真正的降低測試整合的成本、縮短測試時間，並且所付出的面積也較小。

另一方面，隨著內嵌式記憶體數量及密度的快速成長，記憶體的測試也逐漸在系統晶片測試上占重要的地位。為了減少測試的成本，我們也發展出一個記憶體自我測試電路自動產生器的工具---BIST for RAM in Seconds，簡稱BRAINS。BRAINS的目標在解決系統晶片中大量且不同種類記憶體的測試整合，並做到自動化。同時可以自動將所以的記憶體做分類，達到測試時間、效能、以及功率消耗的較佳化。由於提出的記憶體自我測試電路具有可擴充，與可配置的特性，可以很容易解決各種記憶體測試整合的問題，減少系統晶片設計者在記憶體測試方面的精力。

藉由提出的系統晶片測試整合平台以及記憶體自我測試產生器，可以解決系統晶片中的數位邏輯元件以及記憶體的測試問題。兩者的結合更可以大大的降低系統晶片測試整合的成本。

IPs and memory cores are two key components in system-on-chip (SOC). The reuse of IP cores results in test integration challenges. In addition, the usage of mass heterogeneous memory cores in SOC also increases the cost of memory testing. These two issues make the test cost, especially that related to test integration, one of the major costs in SOC development. How to reduce the cost of logic core and memory testing becomes an important subject so far as SOC development is concerned.

Although there have been plenty of research works on individual topics about SOC testing, few of them took into account the practical integration issues. The proposed Test Access Control System (TACS) allows easy test integration. Based on the IEEE P1500 Test Wrapper, a flexible test access mechanism (TAM) and the associated test controller are developed. In addition, an SOC test integration platform—SOC Test Aid Console, called STEAC—is also proposed to integrate SOC testing automatically. The proposed test architecture (TACS) and integration platform
(STEAC) also solve the practical SOC test integration issues, including real problems found in test scheduling, test I/O reduction, timing of functional test, scan I/O sharing, etc. A test scheduling model is proposed based on our test architecture and test access mechanism (TAM), considering I/O resource constraints. Detailed scheduling further reduces the overall test time of the system chip. In addition, a test wrapper architecture is presented, which supports the coexistence of scan test and functional test. The test integration platform has been applied to an industrial SOC case. Based on the design experience and simulation results, our approach is simple and efficient—low test integration cost, short test time, and small area overhead.

In addition, memory testing is becoming the dominant factor in testing a SOC, with the rapid growth of the size and density of embedded memories. To minimize the test effort, we present an automatic generation framework of memory built-in self-test (BIST) cores for SOC designs—BIST for RAM in Seconds, called BRAINS. BRAINS targets automatic test integration of multiple and heterogeneous memory cores in an SOC environment. The automatic test grouping ptimizes the overhead in test time, performance, power consumption, etc. With a configurable and extensible architecture, the proposed framework facilitates easy memory test integration for core providers as well as system integrators.

With the proposed SOC test integration platform (STEAC) and BIST generation framework (BRAINS), the core test reuse and heterogeneous memory testing in SOC can be solved. Both help
reducing the test integration cost. In addition, the integration of logic core testing and memory core testing is presented. A centralized test controller can handle the testing of logic cores and memory cores. This further reduces the test cost in SOC test integration.

1 Introduction 1
2 SOC Test Challenges 6
3 Core-Based SOC Testing 17
4 Built-In Self-Test for Multiple Heterogeneous Memories 50
5 SOC Test Integration Platform 62
6 Conclusions and Future Work 71

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