跳到主要內容

臺灣博碩士論文加值系統

(3.231.230.177) 您好!臺灣時間:2021/07/28 22:49
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果 :::

詳目顯示

: 
twitterline
研究生:王志偉
研究生(外文):Chih-Wea Wang
論文名稱:半導體記憶體瑕疵診斷分析系統
論文名稱(外文):FAME: An Advanced Memory Failure Analysis Framework
指導教授:吳誠文
指導教授(外文):Cheng-Wen Wu
學位類別:博士
校院名稱:國立清華大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
畢業學年度:92
語文別:中文
論文頁數:102
中文關鍵詞:瑕疵診斷記憶體測試測試演算法產生器錯誤模型失效分析失效圖樣錯誤樣型
外文關鍵詞:failure analysisdefect diagnosisfault diagnosisfault patternfailure pattern
相關次數:
  • 被引用被引用:0
  • 點閱點閱:209
  • 評分評分:
  • 下載下載:46
  • 收藏至我的研究室書目清單書目收藏:0
瑕疵診斷的技術是半導體產業中關鍵的技術之一,密切地關係到量產的時程及獲利能力。傳統上,記憶體的瑕疵診斷大多仰賴失效圖樣和工程人員的經驗來達成,然而這樣的方法已難滿足現今產品更替的速度。為此我們提出一個半導體記憶體的瑕疵診斷系統來加速瑕疵診斷的時間及精確度。它結合了記憶體偵錯及分析(Memory Error Catch and Analysis, MECA)系統,以及記憶體缺陷診斷(Memory Defect Diagnostics, MDD)系統。記憶體偵錯及分析系統採用以錯誤模型為導向之診斷方法,同時能依需求自動產生測試及診斷演算法。記憶體缺陷診斷系統係採用錯誤樣型為導向之診斷方法,進一步提升了缺陷辨認之精確度。此外,這個診斷系統也包含一個圖形界面的瀏覽器,提供工程人員詳查記憶體之失效圖樣與錯誤樣型和分析的結果。同時我們以展示了運用參數量測配合可測性設計的技術,可更進一步釐清缺陷的位置。
在這篇論文中,我們提出了一個有效且自動化的的缺陷診斷與分析方法,可以迅速且有效率地縮減瑕疵定位之搜尋時間;再佐以可測性設計及參數量測的方法,這個瑕疵診斷系統可以達成非常精確的診斷結果。同時,我們以一個工業界的實際產品作為實驗,與傳統方法相比,能夠在極短時間內達到精準的結果。總結來說,這個系統提供了一個系統化、自動化的方法來加速半導體記憶體的瑕疵診斷及良率提升。
Failure analysis (FA) is one of the key competencies and enables reasonable time-to-market, resulting in higher profit than other competitors. Conventional FA for memories based on bitmaps and the experiences of the FA engineer is time consuming and hard to meet the increasing time-to-volume pressure on semiconductor
products. To reach a profitable yield level rapidly in new
development flow demands an efficient and automatic FA
methodology. An advanced memory failure analysis framework is proposed---the Failure Analyzer for MEmories (FAME), to
facilitate the defect diagnosis and yield ramp-up in system-on-chip (SOC) product development. Our FAME integrates
the Memory Error Catch and Analysis (MECA) system and Memory
Defect Diagnostics (MDD) system. The fault-type based
diagnostics approach used by MECA can improve the efficiency of the test and diagnostic algorithms. Furthermore, we also developed a systematic diagnosis approach based on the novel fault-pattern approach. It is used in the MDD system to improve the defect identification capability. Defect diagnosis and FA can be performed
automatically by using the MDD, reducing the time in yield
improvement. FAME also comes with a powerful viewer for
inspecting the failure patterns and fault patterns. It provides an easy way to narrow down the potential cause of failures and identify possible defects. We also demonstrate the ability of parametric testing for defect-level diagnostics with proper design-for-test support in memories. Combining the proposed framework and parametric testing can achieve excellent diagnostic results. An experiment has been done on an industrial case, demonstrating very accurate results in a much shorter time as compared with the conventional way. The main benefit of FAME is thus an automatic methodology and procedure for accelerating FA and yield optimization for semiconductor memories.
1 Introduction 9
1.1 Motivation and Background . . . . . . . . . . 9
1.2 Objectives . . . . . . . . . . . . . . . . . .12
1.3 Organization. . . . . . . . . . . . . . . . . 13
2 Fundamentals of Memory Diagnostics 14
2.1 Functional Fault Models . . . . . . . . . . . 14
2.2 March Tests for Memories . . . . . . . . . .. 16
2.3 Memory Fault-type Diagnostics . . . . . . . . 18
2.4 Memory Failure Analysis with Failure Patterns 20
3 Overview of the Memory Failure Analysis Framework 22
3.1 Fault Pattern Based Memory Diagnostics . . . 22
3.2 Failure Analyzer for Memories (FAME) . . . . 24
3.2.1 Memory Error Catch and Analysis (MECA) System 25
3.2.2 Memory Defect Diagnostics (MDD) System . . 25
4 MECA System 26
4.1 Memory Fault Simulator: RAMSES . . . .. . . . 26
4.2 Test Algorithm Generator: TAGS . . . . . . . 28
4.3 Error Catch Scheme . . . . . . . . . . . . . 33
4.3.1 Error Catch by Built-In Self-Test (BIST) Circuit 33
4.3.2 Error Catch by External Automatic Test Equipment(ATE) . . . . . . . . . . . . . . . . . . . . 37
4.4 Error Analyzer: ERA . . . . . . . . . . . . . 39
5 MDD System 43
5.1 Defect Analysis and Injection . . . . . . . . 44
5.2 Simulation of Faulty Circuits . . . . . . . 50
5.3 Fault Pattern Generation . . . . . . . . . . 51
5.4 Defect Dictionary Creation . . . . . . . . . 53
5.5 Enhanced Automatic Failure Analysis . . . . . 53
5.5.1 Critical Area Estimation . . . . . . . . . .55
5.5.2 Estimation Results . .. . . . . . . . . . . 56
6 Failure/Fault Pattern Analyzer and Viewer 63
6.1 Failure/Fault Pattern Analyzer . .. . . . . . 63
6.2 Failure/Fault Pattern Viewer . . . . . . . . 66
7 SRAM Design-for-Test (DFT) Techniques 69
7.1 Individual Power Supplies . . . . . . . . . . 70
7.2 Read Current Measurement . . . . . . . . . . 73
7.3 Adjustable WordLine Control . . . . . . . . . 74
8 Experimental Results 77
8.1 Realistic Defect Injection Results . . . . . 77
8.2 Fault Pattern Generation . . . . . . . . . . 78
8.3 Defect Dictionary Generation . . . . . . . . 80
8.4 Defect Diagnostics with DFT Support . . . . 80
8.4.1 Diagnostics of Class 1 . . . . . . . . . . 80
8.4.2 Diagnostics of Class 2 . .. . . . . . . . . 86
8.4.3 Diagnostics of Classes 3 and 4 . . .. . . . 88
8.4.4 Diagnostics of Classes 5 and 6 . . .. . . . 89
8.5 Summary of the Experiments . . . . . . . . . 91
8.6 Results from Industrial Chips .. . . . . . . 91
9 Conclusions and Future Work 96
[1] D. K. Scovel, “Semiconductor industry outlook.” http://www.needhamco.com/, 2003.
[2] Semiconductor Industry Association, “International technology roadmap for semiconductors
(ITRS), 2001 edition,” Dec. 2001.
[3] K.-L. Cheng, C.-W. Wang, J.-N. Lee, Y.-F. Chou, C.-T. Huang, and C.-W. Wu, “FAME:
a fault-pattern based memory failure analysis framework,” in Proc. IEEE/ACM Int. Conf.
Computer-Aided Design (ICCAD), (San Jose), pp. 595–598, Nov. 2003.
[4] R. R. Montanes, J. P. de Gyvez, and P. Volf, “Resistance characterization for weak open
defects,” IEEE Design & Test of Computers, vol. 19, pp. 18–26, Sept.-Oct. 2002.
[5] Y. Zorian, “Embedded infrastructure IP for SOC yield improvement,” in Proc. IEEE/ACM
Design Automation Conf. (DAC), (New Orleans), pp. 709–712, June 2002.
[6] M. Tarr, D. Boudreau, and R. Murphy, “Defect analysis system speeds test and repair of
redundant memories,” Electronics, pp. 175–179, Jan. 12 1984.
[7] J. R. Day, “A fault-driven, comprehensive redundancy algorithm,” in IEEE Design & Test of
Computers, vol. 2, pp. 35–44, June 1985.
[8] R. Dekker, F. Beenker, and L. Thijssen, “Fault modeling and test algorithm development for
static random access memories,” in Proc. Int. Test Conf. (ITC), pp. 343–352, 1988.
[9] S. Naik, F. Agricola, and W. Maly, “Failure analysis of high-density CMOS SRAMs using
realistic defect modeling and Iddq testing,” IEEE Design & Test of Computers, vol. 10,
pp. 13–23, June 1993.
[10] J. Khare and W. Maly, “Inductive contamination analysis (ICA) with SRAM application,” in
Proc. Int. Test Conf. (ITC), (Washington, DC), pp. 552–560, Oct. 1995.
[11] T. M. Mak, D. Bhattacharya, C. Prunty, B. Roeder, N. Ramadan, J. Ferguson, and Y. Jianlin,
“Cache RAM inductive fault analysis with fab defect modeling,” in Proc. Int. Test Conf.
(ITC), pp. 862–871, Oct. 1998.
[12] A. J. van de Goor, Testing Semiconductor Memories: Theory and Practice. Gouda, The
Netherlands: ComTex Publishing, 1998.
[13] A. J. van de Goor and S. Hamdioui, “Fault models and tests for two-port memories,” in Proc.
IEEE VLSI Test Symp. (VTS), pp. 401–410, 1998.
[14] A. J. van de Goor and Z. Al-Ars, “Functional memory faults: a formal notation and a taxonomy,”
in Proc. IEEE VLSI Test Symp. (VTS), pp. 281–289, 2000.
[15] A. J. van de Goor, “Using march tests to test SRAMs,” IEEE Design & Test of Computers,
vol. 10, pp. 8–14, Mar. 1993.
[16] A. J. van de Goor, Testing Semiconductor Memories: Theory and Practice. Chichester, England:
John Wiley & Sons, 1991.
[17] P. Camurati, P. Prinetto, M. S. Reorda, S. Barbagallo, A. Burri, and D. Medina, “Industrial
BIST of embedded RAMs,” IEEE Design & Test of Computers, vol. 12, pp. 86–95, Fall 1995.
[18] K. Zarrineh, S. J. Upadhyaya, and S. Chakravarty, “A new framework for generating optimal
march tests for memory arrays,” in Proc. Int. Test Conf. (ITC), pp. 73–82, 1998.
[19] C.-T. Huang, J.-R. Huang, C.-F. Wu, C.-W. Wu, and T.-Y. Chang, “A programmable BIST
core for embedded DRAM,” IEEE Design & Test of Computers, vol. 16, pp. 59–70, Jan.-Mar.
1999.
[20] C.-F. Wu, C.-T. Huang, and C.-W. Wu, “RAMSES: a fast memory fault simulator,” in Proc.
IEEE Int. Symp. Defect and Fault Tolerance in VLSI Systems (DFT), (Albuquerque), pp. 165–
173, Nov. 1999.
[21] A. Benso, S. D. Carlo, G. D. Natale, and P. Prinetto, “Specification and design of a new
memory fault simulator,” in IEEE Asian Test Symp. (ATS), pp. 92–97, Nov. 2002.
[22] A. J. van de Goor and B. Smit, “Generating march tests automatically,” in Proc. Int. Test
Conf. (ITC), pp. 870–878, 1994.
[23] A. Benso, S. D. Carlo, G. D. Natale, and P. Prinetto, “An optimal algorithm for the automatic
generation of march tests,” in Proc. Design, Automation and Test in Europe (DATE), pp. 938–
943, Mar. 2002.
[24] C.-F. Wu, C.-T. Huang, K.-L. Cheng, and C.-W. Wu, “Simulation-based test algorithm generation
for random access memories,” in Proc. IEEE VLSI Test Symp. (VTS), (Montreal),
pp. 291–296, Apr. 2000.
[25] Y. E. Hong, L. S. Leong,W. Y. Choong, L. C. Hou, and M. Adnan, “An overview of advanced
failure analysis techniques for Pentium and Pentium Pro microprocessors,” Intel Technology
Journal, no. 2, 1998.
[26] J. Segal, A. Jee, D. Lepejian, and B. Chu, “Using electrical bitmap results from embedded
memory to enhance yield,” IEEE Design & Test of Computers, vol. 15, pp. 28–39, May 2001.
[27] V. N. Yarmolik, Y. V. Klimets, A. J. van de Goor, and S. N. Demidenko, “RAM diagnostic
tests,” in Proc. IEEE Int. Workshop on Memory Technology, Design and Testing (MTDT),
(San Jose), pp. 100–102, 1996.
[28] C.-F. Wu, C.-T. Huang, C.-W. Wang, K.-L. Cheng, and C.-W. Wu, “Error catch and analysis
for semiconductor memories using March tests,” in Proc. IEEE/ACM Int. Conf. Computer-
Aided Design (ICCAD), (San Jose), pp. 468–471, Nov. 2000.
[29] D. Niggemeyer and E. Rudnick, “Automatic generation of diagnostic March tests,” in Proc.
IEEE VLSI Test Symp. (VTS), (Marina Del Rey, California), pp. 299–304, Apr. 2001.
[30] V. Vardanian and Y. Zorian, “A march-based fault location algorithm for static random access
memories,” in Proc. IEEE Int. Workshop on Memory Technology, Design and Testing
(MTDT), (France), pp. 62–67, July 2002.
[31] C.-W. Wang, C.-F. Wu, J.-F. Li, C.-W. Wu, T. Teng, K. Chiu, and H.-P. Lin, “A built-in
self-test and self-diagnosis scheme for embedded SRAM,” J. Electronic Testing: Theory and
Applications, vol. 18, pp. 637–647, Dec. 2002.
[32] I. Schanstra, D. Lukita, A. J. van de Goor, K. Veelenturf, and P. J. van Wijnen, “Semiconductor
manufacturing process monitoring using built-in self-test for embedded memories,” in
Proc. Int. Test Conf. (ITC), (Washington, DC), pp. 872–881, Oct. 1998.
[33] J. T. Chen, J. Rajski, J. Khare, O. Kebichi, and W. Maly, “Enabling embedded memory
diagnosis via test response compression,” in Proc. IEEE VLSI Test Symp. (VTS), (Marina Del
Rey, California), pp. 292–298, Apr. 2001.
[34] M. A. Merino, S. Cruceta, A. Garcia, and M. Recio, “SmartBitTM: bitmap to defect correlation
software for yield improvement,” in Advanced Semiconductor Manufacturing Conference
and Workshop, IEEE/SEMI, (Boston), pp. 194–198, Sept. 2000.
[35] C.-W. Wang, K.-L. Cheng, J.-N. Lee, Y.-F. Chou, C.-T. Huang, C.-W. Wu, F. Huang, and
H.-T. Yang, “Fault pattern oriented defect diagnosis for memories,” in Proc. Int. Test Conf.
(ITC), (Charlotte), pp. 29–38, Sept. 2003.
[36] K.-L. Cheng, C.-M. Hsueh, J.-R. Huang, J.-C. Yeh, C.-T. Huang, and C.-W. Wu, “Automatic
generation of memory built-in self-test cores for system-on-chip,” in Proc. Tenth IEEE Asian
Test Symp. (ATS), (Kyoto), pp. 91–96, Nov. 2001.
[37] J.-F. Li and C.-W.Wu, “Memory fault diagnosis by syndrome compression,” in Proc. Design,
Automation and Test in Europe (DATE), (Munich), pp. 97–101, Mar. 2001.
[38] S. Hamdioui and A. J. van de Goor, “An experimental analysis of spot defects in SRAMs: realistic
fault models and tests,” in Proc. Ninth IEEE Asian Test Symp. (ATS), (Taipei), pp. 131–
138, Dec. 2000.
[39] A. Ferris-Prabhu, “Defect size variations and their effect on the critical area of VLSI devices,”
IEEE Journal of Solid-State Circuits, vol. 20, pp. 878–880, Aug. 1985.
[40] C.-W. Wang, C.-F. Wu, J.-F. Li, C.-W. Wu, T. Teng, K. Chiu, and H.-P. Lin, “A built-in selftest
and self-diagnosis scheme for embedded SRAM,” in Proc. Ninth IEEE Asian Test Symp.
(ATS), (Taipei), pp. 45–50, Dec. 2000.
[41] A. J. van de Goor and J. E. Simonse, “Defining SRAM resistive defects and their simulation
stimuli,” in Proc. Eighth IEEE Asian Test Symp. (ATS), (Shanghai), pp. 33–40, Nov. 1999.
[42] A. Meixner and J. Banik, “Weak write test mode: An SRAM cell stability design for test
technique,” in Proc. Int. Test Conf. (ITC), (Washington, DC), pp. 1043–1052, Nov. 1997.
[43] D. L. Wendell, “Memory array test and characterization using isolated cell power supply.”
U.S. Patent No. 5920517, 1999.
[44] D.-M. Kwai, H.-W. Chang, H.-J.Liao, C.-H. Chiao, and Y.-F. Chou, “Detection of SRAM
cell stability by lowering array supply voltage,” in IEEE Asian Test Symp. (ATS), (Taipei),
pp. 268–273, Dec. 2000.
QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top
無相關期刊