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研究生:郭碩芬
研究生(外文):Shyr-Fen Kuo
論文名稱:縮短半導體記憶元件測試時間的方法與快閃記憶體之自我測試電路產生器
論文名稱(外文):Semiconductor Memory Test Time Reduction and Automatic Generation of Flash Memory Built-in Self-Test Circuits
指導教授:吳誠文
指導教授(外文):Cheng-Wen Wu
學位類別:碩士
校院名稱:國立清華大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2004
畢業學年度:92
語文別:中文
論文頁數:98
中文關鍵詞:縮短測試時間快閃記憶體自我測試半導體記憶元件
外文關鍵詞:Test Time ReductionFlash MemoryBuilt-In Self-TestMemory
相關次數:
  • 被引用被引用:0
  • 點閱點閱:320
  • 評分評分:
  • 下載下載:81
  • 收藏至我的研究室書目清單書目收藏:1
在單晶片(SoC)系統的設計上,半導體記憶元件的比重越來越大,因此,半導體記憶元件的測試也日驅重要,隨著半導體記憶元件的面積與速度快速地增加,所需使用的測試時間與測試電路也越來越大。在這篇碩士論文中,我們針對在半導體記憶元件的測試中兩種不同的問題,提出不同的解決方法,第一個問題是關於縮短半導體記憶元件測試時間的方法,另一個事關於快閃式記憶體之自我測試電路產生器。

第一部份,我們提出了一個有系統的方式來縮短半導體記憶元件的測試時間,經由分析與重新整理整體的測試流程,我們可以將原有的測試項目作合併,也可以利用模擬器來發展新的測試項目以增加錯誤涵蓋率(fault coverage)。這個有效率之測試項目可以取代原始的測試項目,節省半導體記憶元件整體的測試時間,而在實驗結果中,證實了所提出之測試項目在不影響整體之錯誤涵蓋率的情況下,有效節省了7%的測試時間。

第二部份,我們提出了一個用於快閃式記憶體的自我測試電路產生器,這個自我測試電路產生器可以根據快閃式記憶體的規格與測試的要求來產生可合成的自我測試電路,並且,自我測試電路的架構將會合併我們以前所作的快閃式記憶體的架構與之前所發展的內嵌式隨機存取記憶體之自我測試電路產生器(稱作BRAINS)的架構,並且提供可程式化的March-like 測試演算法。這個快閃記憶體的自我測試電路產生器可縮短測試電路的設計時間,並且,使用我們所提出的
架構可以方便測試排程(test scheduling)的控制。
Semiconductor memories play an important role in modern System-on-Chip (SoC) designs, including RAM and Flash memory. Semiconductor memory testing thus has been a key problem in testing integrated circuits for years. With their growing density and capacity, the test time grows rapidly if the test methodologies and equipments remain the same. Test time reduction other than parallel insertion—which is expensive and more and more difficult to keep up with the memory capacity growth—is a long time researched issue, as test cost is directly related to the time each
product stays on the tester. Furthermore, we also need more design-for-testability (DFT) circuits to reduce the memory test time in the SoC era. The designers need to pay more attention to designing the DFT circuits.

In this thesis, there are two parts devoted solving the memory testing issues discussed above. One is semiconductor memory test time reduction. We propose a systematic pproach to analying and rearranging the test items in the test flow. We propose two test compaction techniques: 1) merging existing test patterns, 2) developing efficient new test patterns. The proposed test time reduction algorithm is shown to effectively reduce the test time of an industrial DRAM test flow. The test time reduction tool also can identify the redundant test items, suggest a proper test list, and provide the correlation between the test items. In the industrial case, an extra 7% of the total test time is further reduced, on top of the original manually compacted test flow.

The other is the Flash memory built-in self-test (BIST) circuit generator. This generator can generate synthesizable BIST RTL code in Verilog, and the generated BIST can combine with RAM BIST that is generated by a RAM BIST generator (called BRAINS). Besides, the generated BIST
architecture supports paralled testing of multiple Flash memory cores to reduce test time in SoC.
摘要....... .......................................... 1
誌謝...... ........................................... 2
目錄..... ............................................ 3
第一章 導論........................................... 4
第二章 背景資料與回顧................................. 5
第三章 縮短半導體記憶元件測試時間的方法............... 6
第四章 縮短半導體記憶元件測試時間自動化............... 7
第五章 縮短半導體記憶元件測試時間的實驗結果........... 8
第六章 整合隨機存取記憶體與快閃記憶體之自我測試電路... 9
第七章 快閃記憶體之自我測試電路產生器................ 10
第八章 快閃記憶體之自我測試電路產生器的實驗結果...... 11
第九章 結論與未來展望................................ 12
英文附錄 ............................................ 13
[1] J. E. Vollrath, “Testing and characterization of SDRAMs,” in IEEE Design & Test of Computers, pp. 42– 50, Feb. 2003.
[2] C. Cheng, C.-T. Huang, J.-R. Huang, C.-W. Wu, C.-J. Wey, and M.-C. Tsai, “BRAINS: A BIST complier for embedded memories,” in Proc. IEEE Int. Symp. Defect and Fault Tolerance in VLSI Systems (DFT), (Yamanashi), pp. 299–307, Oct. 2000.
[3] K.-L. Cheng, C.-M. Hsueh, J.-R. Huang, J.-C. Yeh, C.-T. Huang, and C.-W. Wu, “Automatic generation of memory built-in self-test cores for system-on-chip,” in Proc. Tenth IEEE Asian Test Symp. (ATS), (Kyoto), pp. 91–96, Nov. 2001.
[4] J.-C. Yeh, C.-F. Wu, K.-L. Cheng, Y.-F. Chou, C.-T. Huang, and C.-W. Wu, “Flash memory built-in self-test using march-like algorithms,” in Proc. IEEE Int. Workshop on Electronic Design, Test, and Applications (DELTA), (Christchurch), pp. 137–141, Jan. 2002.
[5] P. Bernardii, M. Rebaudengo, M. S. Reorda, and M. Violante, “A P1500-compatible programmable BIST approach for the test of embedded flash memories,” in Proc. Design, Automation and Test in Europe (DATE), (Munich), pp. 720–725, Mar. 2003.
[6] C.-T. Huang, J.-R. Huang, C.-F. Wu, C.-W. Wu, and T.-Y. Chang, “A programmable BIST core for embedded DRAM,” IEEE Design & Test of Computers, vol. 16, pp. 59–70, Jan.-Mar. 1999.
[7] P. Cappelletti, C. Golla, P. Olivo, and E. Zanoni, Flash Memories. Boston: Kluwer Academic Publishers, 1999.
[8] K.-L. Cheng, J.-C. Yeh, C.-W. Wang, C.-T. Huang, and C.-W. Wu, “RAMSES-FT: A fault simulator for flash memory testing and diagnostics,” in Proc. IEEE VLSI Test Symp. (VTS), (Monterey, California), pp. 281–286, Apr. 2002.
[9] IEEE, IEEE 1005 Standard Definitions and Characterization of FloatingGate Semiconductor Arrays. Piscataway: IEEE Standards Department, 1999.
[10] A. K. Sharma, Semiconductor Memories: Technology, Testing, and Reliability. Piscataway: IEEE Press, 1997.
[11] M. G. Mohammad, K. K. Saluja, and A. Yap, “Testing flash memories,” in Proc. 13th Int. Conf. VLSI Design, pp. 406–411, Jan. 2000.
[12] M. G. Mohammad and K. K. Saluja, “Flash memory disturbances: modeling and test,” in Proc. IEEE VLSI Test Symp. (VTS), (Marina Del Rey, California), pp. 218 –224, Apr. 2001.
[13] S.-K. Chiu, J.-C. Yeh, C.-T. Huang, and C.-W. Wu, “Diagonal test and diagnostic schemes for flash memories,” in Proc. Int. Test Conf. (ITC), (Baltmore), pp. 37–46, Oct. 2002.
[14] A. J. van de Goor, Testing Semiconductor Memories: Theory and Practice. Chichester, England: John Wiley & Sons, 1991.
[15] C.-F. Wu, C.-T. Huang, and C.-W. Wu, “RAMSES: a fast memory fault simulator,” in Proc. IEEE Int. Symp. Defect and Fault Tolerance in VLSI Systems (DFT), (Albuquerque), pp. 165–173, Nov. 1999.
[16] C.-F. Wu, C.-T. Huang, K.-L. Cheng, and C.-W. Wu, “Simulation-based test algorithm generation for random access memories,” in Proc. IEEE VLSI Test Symp. (VTS), (Montreal), pp. 291–296, Apr. 2000.
[17] W.-J. Wu, C.-Y. Tang, and M.-Y. Lin, “Methods for memory test time reduction,” in Proc. IEEE Int. Workshop on Memory Technology, Design and Testing (MTDT), pp. 64–70, Aug. 1996.
[18] W.-J. Wu and C.-Y. Tang, “Memory test time reduction by interconnecting test items,” in IEEE Asian Test Symp. (ATS), pp. 290–298, Dec. 2000.
[19] M. R. Garey and D. S. Johnson, Computers and Intractability: A Guide to the Theory of NP-Completeness. San Francisco: W. H. Freeman, 1979.
[20] R. A. Brualdi and V. Pless, “Greedy codes,” in Proc. IEEE Int. Symp., pp. 366– 366, Jan. 1993.
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