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研究生:郭銘彬
研究生(外文):Min-Pin Kuo
論文名稱:深次微米缺陷之路徑延遲診斷技術
論文名稱(外文):Diagnosing Deep SubMicron Defects For Path Delay Fault
指導教授:劉靖家
指導教授(外文):Jing-Jia Liou
學位類別:碩士
校院名稱:國立清華大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2004
畢業學年度:92
語文別:英文
論文頁數:56
中文關鍵詞:延遲診斷
外文關鍵詞:delay diagnosis
相關次數:
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延遲診斷 (delay diagnosis) 的目的是為了找出最有可能造成延遲錯誤的地方,一個有效率的診斷軟體可以提供設計者一組比較少且需要先檢查的地方,藉以減少重新設計所花費的時間。
在這篇論文中我們已經發展出一種新的延遲診斷方法,首先我們利用多次的測試分別找到每條受測路徑的上限 (upper bound) 和下限時間 (lower bound),然後我們將路徑的延遲時間轉換成線性方程式,當我們解出電路中每個區段的延遲時間 (segment delay) 後,我們可以依據這個結果告訴設計者那些地方是最有可能有延遲錯誤的地方,從實驗的結果中可以看出我們所提出的方法之診斷正確性。
The goal of diagnosis method is to determine the suspected faulty node which is the most probable
cause of the observed failures. An efficient diagnosis tool can drastically reduce the redesign time
by providing the designers with a small set of possible faults to investigate. In this thesis, we have
proposed a method of delay fault diagnosis. We apply a testing methodology [1] to have two times
for every path. These two times, form a lower and upper bound respectively on the delay of path.
We translate the path bound to linear programming equations [2]. We can solve the equations and
use the result for diagnosing delay defect. Then, we simplify the linear programming equation
in advance to improve diagnosis. The experimental result shows the accuracy of our diagnosis
methodology.
1
Contents
1 Introduction 8
1.1 Diagnosis Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.2 Delay Testing Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.3 Applications of Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2 Previous Approaches of Delay fault Diagnosis 13
2.1 Diagnosis Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2 Diagnosis Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2.1 Six-ValuedSimulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.2.2 Multiple delay fault diagnosis . . . . . . . . . . . . . . . . . . . . . . . . 16
2.2.3 Effect-Cause Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.2.4 Bounding Circuit Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.2.5 Diagnosis Using PDFs With Validatable Non-robust Test . . . . . . . . . . 24
2.3 Diagnosis in Sequential Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3 Diagnosis Methodology for Deep Sub-Micron Delay Defects 28
3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.2 An Example to Illustrate the New Diagnosis Method . . . . . . . . . . . . . . . . 33
3.3 SolverResultAnalysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2
3.3.1 Combine Inseparable Segments . . . . . . . . . . . . . . . . . . . . . . . 38
4 Experimental Results 40
4.1 Experimental Assumptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.2 The Experimental Results for Diagnosing Path Delay Fault . . . . . . . . . . . . . 41
4.2.1 TheFirstExperimentalResults . . . . . . . . . . . . . . . . . . . . . . . . 43
4.2.2 TheSecondExperimentalResults . . . . . . . . . . . . . . . . . . . . . . 46
4.2.3 Results of Diagnosing Multiple Delay Faults . . . . . . . . . . . . . . . . 50
5 Conclusions and Future Work 52
5.1 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5.2 FutureWork . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3
List of Figures
1.1 TestingScheme forCombinationalCircuits . . . . . . . . . . . . . . . . . . . . . 10
2.1 Diagnosis Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2 Generate Suspect List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3 ReduceSuspectList . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.4 ExampleCircuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.5 SuspectCircuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.6 LinearRelationsbetweenPathDelays . . . . . . . . . . . . . . . . . . . . . . . . 23
2.7 Diagnosis Using PDFs with a VNR Test (a) Passed test: Pattern I. . . . . . . . . . 25
2.8 Diagnosis Using PDFs with a VNR Test (b) Passed test: Pattern II. . . . . . . . . . 25
2.9 Diagnosis Using PDFs with a VNR Test (c) Passed test: Pattern III. . . . . . . . . 26
3.1 New Diagnosis Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.2 TheExampleof theCircuitC17 . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.3 Inseparable Segments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.4 CombineSegmentRule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.1 ExperimentalFlow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.2 OriginalTopTen&DelaySize . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.3 ImprovedTopTen&DelaySize . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.4 CompareTopTenResult . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.5 Compare Unbounded Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5.1 Unbounded Result Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

List of Tables
2.1 Comparison of Different Delay Fault Models . . . . . . . . . . . . . . . . . . . . 16
2.2 PathsofExampleCircuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3 LocalSuspectSets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.4 SensitizedPDFs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.1 SymbolMappingTable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.2 LinearProgrammingSolverResult . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.3 CombinedSymbolMappingTable . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.1 Combine Inseparable Segments Result . . . . . . . . . . . . . . . . . . . . . . . . 42
4.2 ExperimentalSetup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.3 The number of injected faults without combining inseparable segments . . . . . . . 44
4.4 OriginalTop20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.5 Original Unbounded Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.6 CombinedInjectSegmentFaultNumbers . . . . . . . . . . . . . . . . . . . . . . 46
4.7 Top20 of ImprovementMethod . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.8 The Average Rank of Top Ten . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.9 ExperimentalSetup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.10 Top20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.11 Unbounded Case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.12 Experimental Results for Diagnosing Multiple Faults . . . . . . . . . . . . . . . . 51
5.1 SegmentMappingtable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5.2 Appearance Time and Ranking Result . . . . . . . . . . . . . . . . . . . . . . . . 54
[1] M. Sharma and J. H. Patel, “Bounding Circuit Delay by Testing a Very Small Subset of
Paths”, Proceedings of IEEE VLSI Test Symposium, pp. 333–341, Apr. 2000.
[2] Brian D. Bunday, Basic Linear Programming, Edward Arnold, London, 1984.
[3] A. Krstic and K.-T. Cheng, Delay Fault Testing for VLSI Circuits, Kluwer Academic Publishers,
Boston, MA, 1998.
[4] P. Girard, C. Landrault, and S. Pravossoudovitch, “A Novel Approach to Delay-Fault Diagnosis”,
Proceedings of Design Automation Conference, pp. 357–360, June 1992.
[5] J. G. Dastidar and N. A. Touba, “A systematic Approach for Diagnosing Multiple Delay
Faults”, Symposium on Defect and Fault Tolerance, pp. 211–216, Nov. 1998.
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[7] Y.-C. Hsu and S. K. Gupta, “A New Path-Oriented Effect-Cause Methodology to Diagnose
Delay Failures”, Proceedings of IEEE International Test Conference, pp. 758–767, Oct.
1999.
[8] P. Pant and A. Chatterjee, “Efficient Diagnosis of Path Delay Faults in Digital Logic Circuits”,
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475, Nov. 1999.
[9] P. Pant, Y.-C. Hsu, S. K. Gupta, and A. Chatterjee, “Path Delay Fault Diagnosis in Combinational
Circuits With Implicit Fault Enumeration”, Proceedings of IEEE/ACM International
Conference on Computer-Aided Design, pp. 1226–1335, Oct. 2001.
[10] K. T. Cheng and H. C. Chen, “Delay testing for nonrobust untestable circuits”, Proceedings
of IEEE International Test Conference, pp. 954–961, Apr. 1993.
[11] W. K. Lam, A. Saldanha, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, “Delay fault
coverage and performance tradeoffs”, Proceedings of Design Automation Conference, pp.
446–452, June 1993.
[12] U. Sparmann, D. Luxenburger, K. T. Cheng, and SM. Reddy, “Fast identificationof robust
dependent path delay faults”, Proceedings of Design Automation Conference, pp. 119–125,
June 1995.
[13] K. T. Cheng and H. C. Chen, “Classification and identification of nonrobust untestable path
delay faults”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,
pp. 845–853, Aug. 1996.
[14] S. Padmanaban and S. Tragoudas, “An Implicit Path-Delay Fault Diagnosis Methodology”,
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 1399–
1408, Oct. 2003.
[15] R. C. Tekumalla, S. Venkataraman, and J. G. Dastidar, “On Diagnosing Path Delay Fault
in an At-Speed Environment”, Proceedings of IEEE VLSI Test Symposium, pp. 28–33, Apr.
2001.
[16] Peter Notebaert, “Linear programming solver”, http://groups.yahoo.com/group/lpsolve,
2003.
[17] J. J. Liou, K. T. Cheng, and D. A.Mukherjee, “Path Selection for Delay Testing of Deep Sub-
Micron Devices Using Statistical Performance Sensitivity Analysis”, Proceedings of IEEE
VLSI Test Symposium, pp. 97–104, Apr. 2000.
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