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研究生:蘇明毅
研究生(外文):Ming-Yi Sum
論文名稱:利用功率模式分析及功能性權值計算法估測暫存器轉換層次功率消耗
論文名稱(外文):RTL Power Estimation Using Power Mode Classification and Functional Weighting
指導教授:黃錫瑜黃錫瑜引用關係
指導教授(外文):Shi-Yu Huang
學位類別:碩士
校院名稱:國立清華大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2004
畢業學年度:92
語文別:中文
論文頁數:71
中文關鍵詞:功率評估暫存器轉移階層
外文關鍵詞:Power EstimationRTL
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近年來,功率消耗成為了IC設計中非常重要的一個課題。這主要是因為過大的功率消耗,會導致電路過熱,使得電路的效能大打折扣。為了處理今日越來越複雜的晶片密度,電路在設計的階段中,能夠越早知道電路的消耗,越能夠在早期幫助設計者做功率上的最佳化設計。如此的最佳化設計,能夠在越高的層次執行,所節省的功率消耗更顯著。
基於上述種種,電路的功率評估工具對於設計者而言,是非常重要的。但不幸地,一般的功率評估工具在評估功率時,都需要在比較低階的層次,例如邏輯閘階層,如此一來會消耗蠻多的時間來做評估,對於設計者而言,功率最佳化的工作,也變得只有較少的選擇。因此,我們發展了一個建立在暫存器轉移階層,並且能夠快速評估功率兼具準確度的方法。主要我們分為兩個階段,第一個階段為功率模型的建立,第二個階段則為功率評估階段。首先我們將電路的行為模式細分出來,根據這些行為模式以及我們拿來使用建立模型的功能性樣本,建立起預測電路的模型。一旦在模型建立好後,進入了功率評估的階段,我們將功能性樣本依其操作的行為模式以及型態,帶入我們的功率模型,最後可以求得最終的功率消耗。
實驗的結果發現,我們所建立的暫存器轉移階層的功率模型,能夠得到準確的功率消耗,在我們測試的十一個電路中,得到的平均誤差為3.82%.
RT-level power estimation is to quickly predict the total switching activity in a logic design without resorting to the time-consuming gate-level simulation. This thesis investigates an RTL power estimation methodology suitable for large designs. In order to retain high accuracy, a number of features are proposed, including a power mode classification method and a functional-weighting scheme for linear approximation. Furthermore, in order to take into account the temporal and spatial correlations among the input patterns, we use a cycle-by-cycle modeling scheme. On top of it, each primary input is further encoded into two binary variables to faithfully reflect its switching behavior. The proposed method has been realized as a practical tool that can fit into the commercial design flow and tested by a number of real designs. Experimental results show that the average estimation error as compared to full gate-level simulation is only 3.82%.
1. Introductions 7
1.1 Motivation……...…………….……………………………………………......8
1.2 Organization……………………………………………...…………………...12

2. Preliminary 13
2.1 RT-level power estimation techniques…………………………………….…..13
2.1.1 Analytical power models……………………………………….......….13
2.1.2 Characterization-based macro-model……………………….………....14
2.1.3 Control logic analysis techniques………………………….…………..15
2.2 Power consumption components…………………………………….………..15
2.2.1 Static power consumption…………………………………….....………16
2.2.2 Dynamic power consumption…………………………....…….………..18

3. Improved Linear Approximation 20
3.1 Statement of the problem………………………………….…………...……...20
3.1.1 Power model format…………………………………………………..…21 3.2 Up-down encoding…………………………………………………………….22
3.3 The main restrictions on up-down encoding scheme………………………….27

4. Overall Flow 29
4.1 Power mode identification………………………………………….………....29
4.1.1 Build hierarchical module tree of the circuit………………….………...29
4.1.2 Build power mode tree of every module……………………….…….…31
4.1.3 Analyze the VCD file………………………………………….………..33
4.2 Power model using functional weighting…………………………….……….35
4.2.1 Constructing fan-out cones of each input……………………….………36
4.2.2 Calculating functional weights………………………………….………37

5. Implementation 43
5.1 System overview………………………………………………………….…..44
5.1.1 Data preparation……………………………………………….………..44
5.1.2 Modeling phase………………………………………………....………45
5.1.3 Extrapolation phase………………………………………………….….47

6. Experimental Results 49
6.1 Usage of our tool………………………………………………………………49
6.2 Experiments………………………………………………………….………..51
6.2.1 Circuits elaborated from DesignWare………………………….……….51
6.2.2 Greatest-common-divisor circuit……………………………….……….55
6.2.3 Montgomery inverse circuit…………………………………….……….57
6.2.4 Finite impulse response filter…………………………………….…..….60
6.2.5 Arithmetic encoder………………………………………………...…….62
6.2.6 A symmetric crypto processor (AES)…...………………………….……65

7. Conclusion 67

8. Bibliography 68
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