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研究生:陳柏霖
研究生(外文):Po-Lin Chen
論文名稱:功能性路徑延遲錯誤測試自動化限制產生
論文名稱(外文):The Automation of Constraint Extraction for Functional Path Delay Fault Testing
指導教授:張慶元張慶元引用關係
指導教授(外文):Tsin-Yuan Chang
學位類別:碩士
校院名稱:國立清華大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2004
畢業學年度:92
語文別:中文
論文頁數:45
中文關鍵詞:功能性限制延遲路徑樣本產生
外文關鍵詞:Functional ConstraintsPath DelayTest Pattern Generation
相關次數:
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  • 下載下載:6
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隨著積體電路製程技術的進步,從0.25微米製程進入0.18甚至是0.09深次微米製程,也因此導致關於時序(Timing)所引起的製程缺陷(Manufacturing Defects)將漸漸的主宰了晶片的良率(Yield),然而,利用傳統針對Stuck-at Fault所加入可測試性設計(Design for Testability)的測試方法,諸如掃描串聯測試(Scan Chain Testing)以及內建自我測試(Built-in Self-testing)來測試時序缺陷並不適合。此外,針對上述方法缺點而研發的軟體介面功能性測設(Software-based Functional Testing)在處理較複雜的大型電路,例如處理器(Processors)或是功能導向積體電路(ASICs)卻顯得費時而無效率可言。在此篇論文,我們提出一個改善軟體介面功能性測試缺點並針對時序缺陷之一的路徑延遲錯誤(Path Delay Fault)的功能性路徑延遲性錯誤測試流程(Functional Path Delay Fault Test Flow),並且針對較複雜
功能性限制的擷取(Functional Constraints Extraction)加以自動化。
測試的流程主要分成四個部分,第一部分,根據路徑延遲測試的定義將一個循序數位邏輯電路(Sequential Logic Circuit)自動分割成數個管線級(Pipeline Stage).第二部分,則是藉由自動分析硬體描述語言(RTL code),處理器指令集(Instruction Set Architecture)以及測試樣板(Testbench),以萃取出每個管線級可能的輸入限制(Inputs Constraints),這些限制描述著微處理器在執行指令的過程可能的輸入組合.接著在第三部分,利用兩套商業軟體作為輔助,藉由TetraMax針對PrimeTime所擷取出的延遲路徑來作自動樣本的產生(Automatic Test Pattern Generation),所得到的測試樣本(Test Patterns)將與第二部分所萃取的功能性限制作比對與篩選,將符合的限制條件的測試樣本篩選出來.第四部份為測試樣本轉換(Test Patterns Translation),將符合條件的測試樣本轉合成為一個可執行的程式,經由測試程式將測試樣本輸送到帶測管線級作測試。最後本文以Parwan處理器進行測試流程的開發與驗證,以自動化的提升次是流程效率。
With the advantages of at-speed testing, functional mode operation and low area overhead, functional self-test approach is wildly adopted nowadays for delay fault testing. However, modern designs will make this approach hard to apply due to large gate counts and complex functionality. Thus, a modified functional test flow is proposed by this paper to test processors and could be extended to ASICs. This flow includes circuit partition, constraints extraction, pattern generation and back-trace. Each part of the proposed flow is more automatic and effective than other method. The experiment result is demonstrated by testing Parwan processor. And the result showed is good by the proposed method.
Abstract 1
Contents 2
List of Figures 4
List of Tables 5
Chapter 1 Introduction 6
Chapter 2 Preliminaries 10
2.1 Previous Works 10
2.1.1 Test Generation for Gigahertz Processors Using an Automatic Functional Constraints Extractor 11
2.1.2 A Novel Methodology for Hierarchical Test Generation using Functional Constraints Composition1 12
2.1.3 FACTOR: A Hierarchical methodology for Functional Test Generation and Testability Analysis 14
2.1.4 Test Program Synthesis for Path Delay Faults in Microprocessor Cores 16
2.2 Open Problems 18
Chapter 3 Proposed Functional Path Delay Fault Test Flow 20

Chapter 4 The Detail Explanation 24
4.1 Automatic Circuit Partition 24
4.2 Automatic Constraints Extraction 26
4.2.1 Constraints Extraction Method 26
4.2.2 Combine Spatial and Temporal Constraints 34
4.3 Automatic Test Patterns Generation 34
4.4 Automatic Back Trace Test Patterns 35
Chapter 5 Experiment Results and Comparisons 37
Chapter 6 Conclusions and Future Works 41
6.1 Conclusions 41
6.2 Future Works 41
Bibliography 45
[1] The National Technology Roadmap for Semiconductors, Semiconductor industry Association, 1977
[2] “National Science Foundation Workshop on Future Research Directions in Testing of Electronic Circuits and Systems,” http://yellow-stone.ece.ucsh.edu/NSF_ WORK SHOP, 1998
[3] C. J Lin, Y. Zorian, and S. Bhawmik, “Integration of Partial-Scan and Built-In Self-Test,” Journal of Electronics Testing: Theory and Applications, 7(1-2): pp. 125-137, August 1995.
[4] W.-C. Lai, A.Kritic and K.T Cheng, “Test Program Synthesis for Path Delay Faults in Microprocessor Cores,” Proc. of Int’l Test Conf., pp 1080-1089, 2000.
[5] J. Shen and J.A. Abraham, “Native Mode Functional Test Generation for Processors with Application to Self Test and Design Validation,” Proc. of the Int’l Test Conf., pp. 990-999, 1998.
[6] K. Batcher and C. Papachristou, “Instruction Randomization Self Test for Processor Cores,” Proc. of the VLSI Test Symp., pp.34-40, 1999.
[7] Li Chen and Sujit Dey, “Software-based Self-Testing Methodology for Processor Cores”, IEEE Trans, on CAD of Integration Circuits and Systems, Vol. 20, no.3, pp.369-380, March 2001.
[8] N. Krantis, D. Gizopoulos, A. Paschalis, and Y. Zorian, “Instruction –Based Self-Testing of Processor Cores”, Proc. of the VLSI Test Symp., pp 233-228, 2002.
[9] N. Krantis, A. Paschalis, D. Gizopoulos, and Y. Zorian, “Instruction-Based Self-Testing of Processor Cores”, Journal of Electronic Testing: Theory and Application (JETTA) 19, pp 103-112, 2003.
[10] Li Chen, S. Ravi, A. Raghunath, and S. Dey, “A Scalable Software-Based Self-Test Methodology for Programmable Processors”, Proc. of the Design Automation Conf., ACM Press, pp. 548-553, 2003.
[11] R. S. Tupuri and J. A. Abraham, “A Novel Functional Test Generation Method for Processors using Commercial ATPG”, Proc. of Int’l Test Conf., pp. 743-752, Nov. 1997.
[12] V. Singh, M. Inoue, K. K. Saluja, and H. Fujiwara, “Instruction-Based Delay Fault Self-Testing of Processor Cores”, Proc. of Int’l Conf. on VLSI Design, pp. 933-938, 2004.
[13] H.-H., Lee “A Self-Test Methodology of Functional Path Delay Fault on Embedded Processor” MS Thesis, Dept. of EE, National Tsing Hua Uuniv., 2003.
[14] R. S. Tupuri, A. Krishnamachary and J. A. Abraham, ”Test Generation for Gigahertz Processors using an Automatic Functional Constraint Extractor,” Proc. 36th Design Automation Conf., pp. 647-652, June 1999.
[15] V. M. Vedula and J. A. Abraham, “A Novel Methodology for hierarchical Test Generation using Functional Constraint Composition,” Proc. IEEE Int’l high-Level Design Validation and Test Workshop, pp. 9-14, November 2000.
[17] Synopsys, Inc. “PrimeTime User Guide”, Version 2002.03, March 2002.
[18] Synopsys, Inc. “TetraMAX® ATPG User Guide”, Version U-2003.06, June 2003.
[19] W.-C. Lai, A. Krstic, and K.-T. Cheng, “On Testing the Path Delay Faults of a Microprocessor Using its Instruction Set”, Proc. of the VLSI Test Symposium, pp. 15-20, 2000.
[20] W.-C. Lai, A.Krstic, and K.-T. Cheng, “Functionally Testable Path Delay Faults on a Microprocessor”, IEEE Design & Test of Computers, pp 6-14, Oct-Dec 2000.
[21] v2html, “Rough Verilog Parser,” Version 6.0, www.burbleland.com/vwhtml/rvp.htm.
[22] P.S Huang, “The ATPG for Functional Path Delay Fault” MS Thesis, Dept. of EE, National Tsing Hua Uuniv., 2004.
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