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研究生:黃喬楠
研究生(外文):Qiao-Nan Huang
論文名稱:利用記憶體分解降低功率之JPEG2000編碼器設計
論文名稱(外文):Power Reduction of A JPEG2000 Encoder Using Memory Decomposition
指導教授:黃錫瑜黃錫瑜引用關係
指導教授(外文):Shi - Yu Huang
學位類別:碩士
校院名稱:國立清華大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2004
畢業學年度:92
語文別:中文
論文頁數:72
中文關鍵詞:JPEG2000 編碼器小波轉換方塊編碼器
外文關鍵詞:JPEG2000 encoderDWTEBCOT
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JPEG2000是一個新制訂完成的靜態影像壓縮標準,比目前通用的JPEG標準有更高的壓縮率,並且可以支援許多新且實用的功能。目前,JPEG2000的硬體架構設計已成為數位相機的關鍵技術。
在這本論文中,我們提出完整的JPEG2000 編碼器的架構並且發展改良過的記憶體分解軟體(memory decomposition tool)進行JPEG2000 編碼器功率最佳化。這個軟體精確度方面改善了過去粗糙的方法,例如,我們建立精確功率模組,包括額外的解碼器、輸出多工器、位址驅動能力與每一個小的記憶體,來完成記憶體分解的方法,有了這些精確的功率模組,我們使用實際可行的搜尋方法來決定最佳的分割數目,針對任何功率消耗大的記憶體。
在實驗中, 我們證明利用記憶體分解軟體應用在JPEG2000編碼器,大約降低30% 的功率消耗。
JPEG2000 is a new still image compression standard. It has better compression performance than conventional JPEG standard, and it provides many useful features. The hardware implementation of JPEG2000, therefore, becomes essential technique of digital still camera. In this thesis, we have implemented a complete JPEG2000 encoder and performed power minimization on this design through an improved memory decomposition tool we developed. This tool is a refinement over previous methods in a number of aspects. For example, we build more accurate power models for the building blocks supporting memory decomposition methodology, including the external bank decoder, output multiplexor, address driver, and each memory sub-bank. With such accurate power models, we can then embark on a realistic search to decide the optimal bank number for decomposing an arbitrary given large memory. The experiments results show that about 30% power reduction can be achieved when utilizing this memory decomposition tool for our JPEG2000 encoder.
1 Introduction 7
1.1 JPEG-2000 Overview…………………………………………...7
1.2 Motivation……………………………………………………….9
1.3 Thesis Organization……………………………………………..9

2 Overview of JPEG2000 Encoding Algorithm 10
2.1 Lifting-Based Wavelet Transform……………….……………..10
2.2 Context Formation of EBCOT…………………………………14
2.2.1 Concepts…………………………………………………15
2.2.2 Fractional bit-plane coding: Three coding passes……….18
2.2.3 Four types of context formation…………………………19
2.3 Adaptive Context-Based Arithmetic Encoder………………….24

3VLSI Architecture for JPEG2000 Encoder 27
3.1 VLSI Architecture for Lifting-Based DWT…………………….27
3.1.1 1-D discrete wavelet transform…………………………..27
3.1.2 2 -D discrete wavelet transform………………………….29
3.2 VLSI Architecture for Context Formation……………………...29
3.2.1 Column-Based Operation………………………………..30
3.2.2 Memory Arrangement……………………………………31
3.2.3 The Bit-plane Module……………………………………34
3.2.4The Context Formation module…………………………..35
3.3 VLSI Architecture of Adaptive Arithmetic Coder……………...37

4 Memory Decomposition for Power Reduction 39
4.1 Memory Decomposition for Low Power……………………….40
4.2 Flow of power-conscious memory decomposition......................43
4.2.1 Memory Power Model…………………………………...44
4.3.2 The Logic Circuit Power Model…………………………46
4.3 Recursive Partitioning algorithm…………………………….…48
4.4 Implementation…………………………………………………51

5 Experimental Results 53
5.1Implement of JPEG2000 encoding ……………………….…….53
5.2Experimental result of memory decomposition…………………55

6 Conclusion 69
Bibliography 70
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