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研究生:賴國欣
研究生(外文):Kuo-Hsin Lai
論文名稱:消除比較器的雜訊應用於CMOS影像感測器設計
論文名稱(外文):Noise Reduction Of A Comparator In A CMOS Image Sensor Design
指導教授:黃錫瑜黃錫瑜引用關係
指導教授(外文):Shi-Yu Huang
學位類別:碩士
校院名稱:國立清華大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2004
畢業學年度:92
語文別:中文
論文頁數:50
中文關鍵詞:影像感測器雜訊比較器
外文關鍵詞:CMOS Image SensorNoisecomparator
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在現代生活中,數位影像系統扮演著一個很重要的角色,影像感測器可以提供給我們視覺及溝通上的便利,數位相機、網路攝影機便是很好的例子。拿現在兩大主流:電子耦合式(CCD)影像感測器和互補式金氧半導體式影像感測器(CMOS Image Sensor)做比較,對互補式金氧半導體式影像感測器而言,雖然有動態範圍較低、雜訊較大的問題,但是它的耗電量低、整合度高的優勢,是值得我們去做深入研究。
本篇論文提出以一個消除雜訊的比較器所設計而成的互補式金氧半導體式影像感測器。我們利用零偏差、低成本的比較器來完成這個設計,因為這種型式的比較器不需要運算放大器,也就因此有這樣的優點。電荷注入雜訊(Charge Injection Noise)是降低比較器的解析度一個最大的問題,我們的研究中發現,適當調整比較器中電晶體的大小,可以顯著地降低電荷注入雜訊,同時提高比較器的解析度。因此,我們提出了兩個搜尋電晶體最適當大小的方法:(1)徹底搜尋的方式,(2)篩選淘汰的方式。我們實際利用上述兩種方法找出的尺寸大小,實現在一建立於類比至數位轉換器中的比較器來呈現出這個方式的影響程度,並利用此類比至數位轉換器,完成影像感測器的設計。利用電路佈局後的結果來做比較,最後的實驗結果會證明這個方法確實能將解析度提高,並適用在設計比較器的用途上。
In this thesis, noise-reduction of a comparator in a CMOS image sensor design is investigated. This comparator is low-cost and offset-free. The charge injection noise is the only issue that needs to be addressed, because it reduces the resolution of the comparator significantly. Our investigation shows that the charge injection noise can be alleviated significantly by simply sizing the transistors inside this comparator properly. We propose two methods to search for the optimal size: (1) exhaustive method and (2) screening method. An Analog-To-Digital Converter (ADC) incorporating this comparator in a CMOS image sensor design is used as a vehicle to demonstrate the effectiveness. Experimental results show that this methodology does serve as a valuable design aid that can boost the resolution of our image sensor to a desired level.
Abstract…………………………………………………………………1
Contents…………………………………………………………………2
List of Figures…………………………………………………………4
List of Tables…………………………………………………………6
Chapter 1 Introduction………………………………………………7
1.1 Motivation…………………………………………………………8
1.2 Thesis Organization………………………………………………9
Chapter 2 Preliminaries……………………………………………10
Chapter 3 Review of A CMOS Image Sensor Design………………14
3.1 A Nonlinear A/D Converter for CMOS Image Sensor………14
3.2 Two-Frame Approach………………………………………………16
3.3 Timing Controller………………………………………………21
3.4 Chip Implementation……………………………………………22
Chapter 4 A Sizing Methodology for A Low-Noise Comparator…24
4.1 Offset-Free Comparator…………………………………………24
4.2 Sizing Methodology………………………………………………28
4.2.1 Exhaustive Method…………………………………………30
4.2.2 Screening Method…………………………………………33
Chapter 5 Experimental Result……………………………………35
5.1 Results of Sizing Methodology………………………………36
5.1.1 Result of Exhaustive Method………………………………36
5.1.2 Result of Exhaustive Method………………………………38
5.1.3 Result of Post-Layout Simulation…………………………40
5.2 Simulation Result………………………………………………41
5.3 Layout………………………………………………………………45
Chapter 6 Conclusion…………………………………………………47
Bibliography……………………………………………………………48
[1] R. H. Nixon, S. E. Kemeny, B. Pain, C. O. Staller, and E .R. Fossum, “256×256 CMOS active pixel sensor camera-on-a-chip”, IEEE Journal of Solid-State Circuits, vol. 31, pp. 2046-2050, December 1996.
[2] E. R. Fossum, “CMOS Image Sensors: Electronic Camera-On-A-Chip”, IEEE Transactions on Electron Devices, vol.44, pp. 1689-1698, October 1997.
[3] S.-F. Chen, Y.-J. Juang, S.-Y. Huang, and Y.-C. King, “Logarithmic CMOS Image Sensor Through Multi-Resolution Analog-To-Digital Conversion,” Proc. Of Int’l Symposium on VLSI Technology, Systems, and Applications, (VLSI-TSA), April 2003.
[4] B.-R. Lin, S.-Y. Huang, C.-H. Lai, and Y.-C. King, "A High Dynamic Range CMOS Image Sensor Design Based On Two-Frame Composition," Proc. of Int'l SOC Conf., pp. 389-392, Sept. 2003.
[5] S. Yang and K. Cho, “High dynamic range CMOS image sensor with conditional reset,” Proc. Of Custem Integrated Circuit Conf., pp.265-268, 2002.
[6] S. Decker, D. McGrath, K. Brehmer, and C. G. Sodini;” A 256×256 CMOS imaging array with wide dynamic range pixels and column-parallel digital output,”, IEEE Journal of Solid-State Circuits, Vol. 33 , No. 12 , pp.2081-2091, Dec. 1998.
[7] O. Yadid-Pecht and E. R. Fossum, ”Wide intrascene dynamic range CMOS APS using dual sampling,” IEEE Transactions on Electron Devices ,Vol. 44 , No. 10 , pp. 1721–1723, Oct. 1997
[8] X. Q. Liu and A. El Gamal, “Simultaneous Image Formation And Motion Blur Restoration Via Multiple Capture,” Proc. Of ICASSP Conf., pp. 1841-1844, May 2001.
[9] D. Yang, B. Fowler, and A. El Gamal, ”A Nyquist rate pixel level A/D converter for CMOS image sensors,” IEEE Journal of Solid-State Circuits ,” Vo.34 , No. 3 , pp.348–356, March 1999.
[10] T. Hamamoto, T. Wakamatsu, and K. Aizawa, “New method of on-sensor A/D conversion,” ISCAS 2001 ,Vol. 4 , pp.6-9, May 2001.
[11] D. A. Johns and K. Martin, “Analog Integrated Circuit Design”, John Wiley & Sons, Inc., 1996.
[12] M. Bruccoleri and P. Cusinato, “Offset Reduction Technique For High-Speed CMOS Comparators,” Electronics Letters, Vol. 32, No.13, pp.1193-1194, 1996.
[13] C.P. Chong and K.C. Smith, “The Design of a High-Resolution CMOS Comparators,” Proc. of Int’l Symposium on Circuits and Systems, Vol. 2, pp. 1427-1430, 1989.
[14] B. Razavi and B.A. Wooley, “Design Techniques For High-Speed, High-Resolution Comparators,” IEEE Journal of Solid-State Circuits, Vol. 27, No. 12, pp. 1916-1926, 1992.
[15] G.M. Yin, F.O. Eynde, and W. Sansen, ”A High-Speed CMOS Comparator With 8-bit Resolution,” IEEE Journal of Solid-State Circuits, Vol. 27, No. 2, pp. 208-211, 1992.
[16] B. Sheu, J.H. Shieh, and M. Patil, “Modeling Charge Injection in MOS Analog Switches,” IEEE Trans. on Circuits and Systems, Vol. 34, No. 2, pp. 214-216, 1987.
[17] L.-W. Lai and Y.-C. King, ”A novel logarithmic response CMOS image sensor with high output voltage swing and in-pixel fixed pattern noise reduction,” 2002 IEEE Asia-Pacific Conference, pp.105– 08, August 2002.
[18] K. Yonemoto and H. Sumi, “A CMOS image sensor with a simple fixed-pattern-noise-reduction technology and a hole accumulation diode,” IEEE Journal of Solid-State Circuits, Vol. 35, No. 8, pp. 1146-1152, December 2000.
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