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研究生:葉人傑
研究生(外文):Jen-Chieh Yeh
論文名稱:快閃記憶體故障模型及測試演算法之研發
論文名稱(外文):Flash Memory Fault Modeling and Test Algorithm Development
指導教授:吳誠文
指導教授(外文):Cheng-Wen Wu
學位類別:碩士
校院名稱:國立清華大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2004
畢業學年度:92
語文別:英文
論文頁數:71
中文關鍵詞:快閃記憶體測試故障模型測試演算法內建自我測試故障模擬程式
外文關鍵詞:Flash Memory TestingFault ModelingTest AlgorithmBuilt-In Self-TestFault Simulator
相關次數:
  • 被引用被引用:1
  • 點閱點閱:373
  • 評分評分:
  • 下載下載:55
  • 收藏至我的研究室書目清單書目收藏:0
快閃記憶體是由一種浮動閘晶體所組成的非揮發性記憶元件,正當我們跨入系統晶片的設計環境時,商用型快閃記憶體及內崁式快閃記憶體的使用也正急遽且快速的成長。然而,傳統的快閃記憶體測試方式不外乎是使用較特定用途之故障模型及測試程式,且傳統之測試流程也是專為特殊設計之快閃記憶體所開發使用。有見於此,我們根據了國際電機/電子工程學會針對浮動閘半導體陣列之特性及定義之標準(IEEE Standard)提出了一套快閃記憶體常見之干擾故障模型。另外,我們也針對位元及字元之快閃記憶體發展出有效率之測試演算法(March-FT),它能有效的測試出快閃記憶體干擾故障及傳統定義之故障。除此之外,我們還開發了故障模擬分析器(RAMSES-FT)方便使用者開發及分析測試演算法之效率。借由測試演算法產生器工具(TAGS)搭配此故障模擬分析器,即可針對使用者希望偵測之故障輕鬆的找出有效率之測試演算法或測試程式。而我們所產生及開發出的測試演算法,都能輕易的移植進內建自我測試電路中,使得我們所開發出之內建自我測試電路皆能針對一般商用之快閃記憶體或內崁式快閃記憶體擁有高效率之測試能力。最後,我們將開發出之內建自我測試電路實際應用於兩個工業界之快閃記憶體,統計出內建自我測試電路之硬體使用量不超出整體總面積之百分之三,足以顯示其耗費之硬體成本極低。
Flash memories are a type of non-volatile memory based on floating-gate transistors. The use of commodity and embedded Flash memories are growing rapidly as we enter the system-on-chip (SoC) era. Conventional fault models and tests for Flash memories are usually ad hoc, and the test procedure is developed for a specific design. We propose a set of disturb fault models that are derived from the IEEE Standard Definitions and Characterization of Floating Gate Semiconductor Arrays. We also propose improved March-like algorithms (i.e., March-FT) for both bit-oriented and word-oriented Flash memories to cover the disturbance faults as well as conventional faults. Besides, a novel Flash memory fault simulator (called RAMSES-FT) is developed to analyze the fault coverage of the test algorithms. The fault simulator is a key component for the test pattern generation tool TAGS, which produces a test to target the fault set that the user specifies. Based on March-FT, we have designed a built-in self-test (BIST) circuit which is suitable for both the commodity Flash memory and embedded Flash core. Finally, we present the BIST designs for two industrial Flash memories, and show the area overhead that is only about 3% for a medium-sized Flash memory.
1 Introduction 1
1.1 Motivation . . . . . . . . . . . . . . . . . . . . 2
1.2 Review of Previous Works. . . . . . . . . . . . . . 3
1.3 Proposed Approach . . . . . . . . . . . . . . . . 4
1.4 Organization . . . . . . . . .. . . . . . . . . 5
2 Flash Memories 7
2.1 Overview . . . . . . . . . . . . . . . .. . . . . . 7
2.2 Basic Operations . . . . . . . . . . . . . . . . . . 9
2.2.1 Read Operation . . . . . . . . . . . . . 10
2.2.2 Program Operation . . . . . . . . . . . . . . 12
2.2.3 Erase Operation . . . . . . . . . . . . . . 12
2.3 Cell Structures . . . . . . . . . . . . . . . . . . 14
2.4 Array Architectures . . . . . . . . . . . . . . . 17
2.5 Common Flash Interface (CFI) . . . . . . . . . . 20
3 Disturb Fault Modeling 22
3.1 Preliminaries . . . . . . . . . . . . . . . . . . . 22
3.2 Program Disturb Faults . . . . . . . . . . . . . . . 22
3.3 Read Disturb Faults . . . . . . . . . . . . . . . . . 25
3.4 Erase Disturb Faults . . . . . . . . . . . . . . . 26
3.5 Conventional Functional Faults . . . . . . . . . . 26
4 Test Algorithm Development 28
4.1 Flash Fault Simulator: RAMSES-FT . . . . . . . . . 28
4.1.1 Basics . . . . . . . . . . . . . . . . . . . . 28
4.1.2 Fault descriptors . . . . . . . . . . . . . . . 30
4.1.3 Fault Coverage Scaling . . . . . . . . . . . . 32
4.2 March-like Tests . . . . . . . . . . . . . . . . 34
ii
4.2.1 March Flash Test (March-FT) . . . . . . . . . . 34
4.2.2 March Flash Diagnosis (March-FD) . . . . . . . 40
4.2.3 Simulation Results andAnalysis . . . . . . . . 42
4.3 Diagonal Tests . . . . . . . . . . . . . . . . . 43
4.3.1 Diagonal Flash Test (Diagonal-FT) . . . . . 44
4.3.2 Diagonal Flash Diagnosis (Diagonal-FD) . . . . 46
4.3.3 Simulation Results andAnalysis . . . . . . . 47
4.4 Test Algorithm Generation by Simulation . . 49
5 Built-In Self-Test Design 51
5.1 BIST Architecture . . . . . . . . . . . . . . . . . 51
5.1.1 Controller (CTR) . . . . . . . . . . . . . 53
5.1.2 Test Pattern Generator (TPG) . . . . . . 56
5.1.3 Multiplexer (MUX) . . . . . . . . . . . 58
6 Experimental Result and Discussions 59
6.1 Experimental Result . . . . . . . . . . . . . . . 59
6.1.1 Embedded Flash Memory Core . . . . . 59
6.1.2 Commodity Flash Memory Chip . . . . . 61
6.2 Discussions . . . . . . . . . . . . . . . . . . . . 64
7 Conclusions and Future Work 65
APPENDIX A RAMSES-FT Manual 67
Bibliography 69
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[17] C.-F. Wu, C.-T. Huang, and C.-W. Wu, “RAMSES: a fast memory fault simulator,” in Proc. IEEE Int. Symp. Defect and Fault Tolerance in VLSI Systems (DFT), (Albuquerque), pp. 165–173, Nov. 1999.
[18] C.-F. Wu, C.-T. Huang, K.-L. Cheng, and C.-W. Wu, “Simulation-based test algorithm generation for random access memories,” in Proc. IEEE VLSI Test Symp. (VTS), (Montreal), pp. 291–296, Apr. 2000.
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