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研究生:鄒善智
研究生(外文):Shan-Chih Tsou
論文名稱:應用於多重標準接收機之金氧半可變增益放大器
論文名稱(外文):CMOS Variable Gain Amplifier for Multi-Standard Receiver
指導教授:黃柏鈞黃柏鈞引用關係
指導教授(外文):Po-Chiun Huang
學位類別:碩士
校院名稱:國立清華大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2004
畢業學年度:92
語文別:中文
論文頁數:62
中文關鍵詞:金氧半可變增益放大器多重標準接收器
外文關鍵詞:CMOSVariable Gain AmplifierMulti-Standard ReceiverVGA
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隨著資料傳輸速率的急速演進,在無線網路基頻段整合具有寬頻寬的類比積體電路方塊將會是一個不可抵抗的未來潮流。另一方面,一個可以應用於多重標準接收機(Multi-Standard Receiver)的單一電路方塊對於加強行動電話的使用度來說是一個相當經濟的實現方式。這篇論文中所提出之應用於多重標準接收機的金氧半(CMOS)可變增益放大器(VGA)就是希望能滿足上述的這兩項趨勢。
一般來說,可變增益放大器是由一個自動增益控制迴路(AGC Loop)所控制。隨著資料傳輸速率的增加,自動增益控制迴路用來作自動增益控制的時間區帶佔一個資料框架(Data Slot)的時間越來越短。為了確保資料傳輸的正確性,一個快速的自動增益穩定(Gain Settling)變得越來越重要。自動增益控制迴路的效能除了需要快速的增益穩定之外,精準的增益穩定,平穩(Stable)的增益
穩定,和低失真的訊號輸出都是重要的效能依據。在這篇論文中,我們建立了一個線性的自動增益控制迴路,並將迴路內可變增益放大器的效能以提出的可變增益放大器效能來取代,然後加以模擬,以了解迴路的動態表現。
另外,在這篇論文中,將針對所提出的一個應用於多重標準接收機的金氧半可變增益放大器作分析、設計、模擬,並以台積電0.18μm 1P6M CMOS 製程技術來加以實作。提出的可變增益放大器的輸出訊號可以維持固定的訊號大小及固定的群延遲(Group Delay)。其頻寬可以由GSM 的100KHz,WCDMA 的2MHz,延伸到WLAN 的10MHz,並且透過設計其頻寬為可調(Adjustable)來增加整體架
構雜訊和線性度的表現。這個可變增益放大器的增益可以由-10dB 變化到20dB,並且其增益變化時,頻寬可以維持一定的特性使得基頻數位訊號處理(DSP)電路得以簡化。此可變增益放大器採用1.8V 的電源供應,整體的功率消耗是2.43mW。晶片的面積是0.645x0.465mm。
With the rapid growth of higher data rate, integrating the analog circuit block with wide bandwidth in the baseband will be an indispensable trend in the future. On the other hand, a single circuit block which can be used for multi-standard receiver is an economic implementation
way to enhance the usability of the cell phone. A CMOS variable gain amplifier (VGA) for multi-standard receiver described in this thesis aims to meet these two demands.
In general, VGA is controlled by an automatic gain control (AGC) loop. As the data rate increases, the data slot which is used for the AGC loop to settle is getting smaller. A fast gain settling of the AGC loop becomes more and more important to make sure the data transfer is correct. The performance of the AGC loop can be characterized not only by a fast gain settling, but also the precise gain settling, the stable gain settling, and a low-distortion output signal. Alinear model of the AGC loop is set up and simulated with the performance of VGA modeled as the proposed one to see the dynamics of the loop.
In this thesis, a proposed VGA for the multi-standard receiver is analyzed, designed, and implemented using the standard 0.18um 1P6M CMOS technology. The output signal of the VGA can be of constant signal level and contant group delay. The bandwidth of the VGA is extended from GSM 100KHz, WCDMA 2MHz to WLAN 10MHz, and designed to be adjustable for the noise and linearity concern of the total architecture. The gain of tha VGA ranges from -10dB to
20dB, and the constant bandwidth peroperty with different gain settings helps the simplification of DSP circuitry in the baseband. The total power consumption of the VGA is 2.43mW at 1.8V supply voltage. The chip area is 0.645mm x 0.465mm.
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